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1. (WO1985004525) A LATCH-UP RESISTANT CMOS STRUCTURE FOR VLSI
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1985/004525 International Application No.: PCT/US1985/000347
Publication Date: 10.10.1985 International Filing Date: 28.02.1985
IPC:
H01L 27/092 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
092
complementary MIS field-effect transistors
Applicants:
HUGHES AIRCRAFT COMPANY [US/US]; 200 North Sepulveda Boulevard El Segundo, CA 90245, US
Inventors:
LEE, William, W.; US
CHANG, Kuang-Yeh; US
Agent:
SZABO, Joseph, E. @; Hughes Aircraft Company Post Office Box 1042, Bldg. C2, M.S. A126 El Segundo, CA 90245, US
Priority Data:
594,58929.03.1984US
Title (EN) A LATCH-UP RESISTANT CMOS STRUCTURE FOR VLSI
(FR) STRUCTURE CMOS RESISTANT AU BLOCAGE POUR INTEGRATION A TRES GRANDE ECHELLE
Abstract:
(EN) A complementary metal oxide semiconductor (CMOS) structure having the source and drain regions (23, 37 and 25, 35) of individual transistor devices separated from the peak impurity concentrations of the respective N- and P-wells (33 and 21) of such devices. The CMOS structure includes trenches (17) between the individual transistor devices, and highly doped field regions (45 and 47) are formed in the bottom of the trenches (17). Each N- and P-well (33 and 21) includes a retrograde impurity concentration profile and extends beneath adjacent trenches (17).
(FR) Structure de semiconducteurs à oxyde métallique complémentaire (CMOS) dans laquelle les régions de source et de drain (27, 37 et 25, 35) des dispositifs à transistors individuels sont séparées des concentrations d'impuretés de crête des puits N et P respectifs (33 et 21) de ces dispositifs. La structure CMOS comprend des tranchées (17) entre les dispositifs à transistors individuels, et des régions de champ hautement dopées (45 et 47) sont formées au fond des tranchées (17). Chaque puits N et P (33 et 21) comprend un profil de concentration d'impuretés rétrograde et s'étend sous des tranchées adjacentes (17).
Designated States: JP
European Patent Office (CH, DE, FR, GB, NL)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0179088