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1. (WO1985004523) CONDUCTIVE, PROTECTIVE LAYER FOR MULTILAYER METALLIZATION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1985/004523 International Application No.: PCT/US1985/000354
Publication Date: 10.10.1985 International Filing Date: 04.03.1985
IPC:
H01L 21/768 (2006.01) ,H01L 23/532 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532
characterised by the materials
Applicants:
ADVANCED MICRO DEVICES, INC. [US/US]; 901 Thompson Place P.O. Box 3453 Sunnyvale, CA 94088, US
Inventors:
BORODOVSKY, Yan, A.; US
Agent:
KING, Patrick, T.; 901 Thompson Place P.O. Box 3453 Sunnyvale, CA 94088, US
Priority Data:
593,33526.03.1984US
Title (EN) CONDUCTIVE, PROTECTIVE LAYER FOR MULTILAYER METALLIZATION
(FR) COUCHE PROTECTRICE CONDUCTRICE POUR UNE METALLISATION MULTICOUCHE
Abstract:
(EN) An integrated circuit structure, and method of making the structure, wherein at least one metallization layer (10) is coated with a conductive indium arsenide layer (12) during production of the structure and an upper metallization layer (40) subsequently is applied to the structure wherein at least a portion of the subsequent metallization layer (40) is in ohmic contact with the conductive indium arsenide layer (12) whereby the lower metallization layer is protected by the intervening indium arsenide layer (12) during subsequent removal of the upper metallization layer if subsequent reworking of the structure becomes necessary. The use of the indium arsenide layer (12) over a metallization layer (10) further enhances the construction process by the use of its antireflective properties during patterning of a photoresist applied over the indium arsenide layer.
(FR) Structure de circuit intégré et procédé de fabrication de cette structure, où au moins une couche de métallisation (10) est enduite d'une couche conductrice d'arséniure d'indium (12) pendant la fabrication de la structure et une couche de métallisation supérieure (40) est appliquée ultérieurement sur la structure où au moins une partie de la couche de métallisation ultérieure (40) est en contact ohmique avec la couche conductrice d'arséniure d'indium (12), la couche de métallisation inférieure étant protégée par la couche interposée d'arséniure d'indium (12) pendant le retrait ultérieur de la couche de métallisation supérieure si un réusinage ultérieur de la structure devient nécessaire. L'utilisation de la couche d'arséniure d'indium (12) sur une couche de métallisation (10) améliore en outre le procédé de fabrication par l'utilisation de ses propriétés antiréfléchissantes pendant le modelage d'un élément photorésistant appliqué sur la couche d'arséniure d'indium.
Designated States: JP
European Patent Office (AT, BE, CH, DE, FR, GB, LU, NL, SE)
Publication Language: English (EN)
Filing Language: English (EN)