An integrated circuit device includes a timing apparatus arranged to produce timing signals whose frequency is a multiple of that of a clock signal. The timing apparatus, which includes a phase locked loop, is formed on a single chip and no external components are necessary. The phase locked loop includes a convertor and filter circuit (11), the convector (14) including two transistor current sources (19, 24) whose current magnitude is determined by a current reference circuit (13) including current mirror transistors (28, 31). The current sources (19, 24) are controlled by increase and decrease output signals from a phase and frequency comparator (7) such that the output of the convertor (14) depends upon the mark space ratio of the comparator output signals. The output of the convertor (14) is filtered and then fed as the control voltage to a voltage controlled oscillator (12). The oscillator output is fed by way of a divider to the phase comparator (7) and also provides the high frequency input timing signal for a logic device, such as a microcomputer (2). As the timing apparatus is fabricated using MOS technology, it is not possible to forecast its performance accurately. Surprisingly, it has been found that the timing apparatus of the invention is capable of exhibiting closed loop stability without further trimming. However, to ensure that such closed loop stability can always be obtained, additional components, for varying the parameters of the circuits may be provided, said components being connectible into the circuit by programmable switches, such as laser fuses (as 33, 42).