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1. WO1985000460 - A BYTE WIDE MEMORY CIRCUIT HAVING A COLUMN REDUNDANCY CIRCUIT

Publication Number WO/1985/000460
Publication Date 31.01.1985
International Application No. PCT/US1984/000757
International Filing Date 17.05.1984
IPC
G11C 29/00 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
CPC
G11C 29/846
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
70Masking faults in memories by using spares or by reconfiguring
78using programmable devices
84with improved access time or stability
846by choosing redundant lines at an output stage
Applicants
  • ADVANCED MICRO DEVICES, INC. [US]/[US]
Inventors
  • YOUNG, Elvan, S.
  • SCHUMANN, Steven, J.
Agents
  • KING, Patrick, T.
Priority Data
514,20314.07.1983US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) A BYTE WIDE MEMORY CIRCUIT HAVING A COLUMN REDUNDANCY CIRCUIT
(FR) CIRCUIT DE MEMOIRE PAR QUARTETS AYANT UN CIRCUIT DE REDONDANCE DE COLONNES
Abstract
(EN)
A 4-bit byte wide memory circuit (12) having a column redundancy scheme including a plurality of bit segments (BS), each having columns (18, 20), for storing data, a plurality of data lines (DL), corresponding, respectively, to the plurality of bit segments (BS), a plurality of I/O ports (PM) coupled, respectively, to the plurality of data lines (DL), a plurality of redundant columns (RC) for storing data and corresponding, respectively, to the plurality of I/O ports (PM), and a programmable circuit (28) for coupling, respectively, the plurality of redundant columns (RC) to one or another of the data lines (DL) while decoupling the bit segments (BS) from the data lines (DL).
(FR)
Un circuit de mémoire par quartets (12) possède un schéma de redondance de colonnes comprenant une pluralité de segments binaires (BS) ayant chacun des colonnes (18, 20), pour le stockage de données, une pluralité de lignes de données (DL) correspondant respectivement à la pluralité de segments binaires (BS) une pluralité de ports entrée/sortie (PM) couplés, respectivement, à la pluralité de lignes de données (DL), une pluralité de colonnes redondantes (RC) pour le stockage de données et de manière correspondante, respectivement à la pluralité de ports entrée/sortie (PM), et un circuit programmable (28) pour coupler entre elles, respectivement, la pluralité de colonnes redondantes (RC) des lignes de données (DL) tout en désaccouplant les segments binaires (BS) des lignes de données (DL).
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Latest bibliographic data on file with the International Bureau