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1. (WO1984000252) POWER BUS ROUTING FOR GATE ARRAYS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1984/000252 International Application No.: PCT/US1983/000890
Publication Date: 19.01.1984 International Filing Date: 06.06.1983
IPC:
H01L 23/52 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/11 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
10
the devices having separate containers
11
the devices being of a type provided for in group H01L29/78
Applicants:
Inventors:
Priority Data:
null30.12.1899null
Title (EN) POWER BUS ROUTING FOR GATE ARRAYS
(FR) ACHEMINEMENT D'UN BUS D'ALIMENTATION POUR DES RESEAUX DE PORTES
Abstract:
(EN) A gate array (10) which has power bus routing for increasing current availability to a plurality of transistor cells (14, 16). The gate array (10) also has separate power busses for input/internal logic and output circuits. The gate array (10) comprises n columns of transistor cells with two power busses (18 and 20) extending substantially along each column to power the cells. Input/internal logic power busses (22 and 24) and separate output power busses (30 and 32) extend around the perimeter of the columns of transistor cells. At least one power strip (36) for increasing current availability to the transistor cells (14, 16) is routed across the transistor cells substantially perpendicular to the n columns and is connected to both the power busses of each column and to the input/internal logic power busses.
(FR) Un réseau de portes (10) possède un bus d'alimentation pour augmenter le courant disponible dans plusieurs cellules de transistors (14, 16). Le réseau de portes (10) possède également des bus d'alimentation séparés pour des circuits de sortie et d'entrée/logique interne. Le réseau de portes (10) comprend n colonnes de cellules de transistors avec deux bus d'alimentation (18 et 20) s'étendant sensiblement le long de chaque colonne pour alimenter les cellules. Des bus d'alimentation d'entrée/logique interne (22 et 24) et des bus d'alimentation de sortie séparés (30 et 32) s'étendent autour du périmètre des colonnes des cellules de transistors. Au moins une bande d'alimentation (36) pour augmenter la disponibilité de courant dans les cellules de transistors (14, 16) est acheminée au travers des cellules de transistors sensiblement perpendiculairement aux n colonnes et est connectée aux deux bus d'alimentation de chaque colonne et aux bus d'alimentation d'entrée/logique interne.
Designated States:
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0112894JPS59501238