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1. (WO1984000088) LEVEL SENSITIVE RESET CIRCUIT FOR DIGITAL LOGIC
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1984/000088 International Application No.: PCT/US1983/000639
Publication Date: 05.01.1984 International Filing Date: 02.05.1983
IPC:
G06F 1/24 (2006.01) ,H03K 17/22 (2006.01) ,H03K 17/795 (2006.01) ,H03K 21/38 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
24
Resetting means
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
17
Electronic switching or gating, i.e. not by contact-making and -breaking
22
Modifications for ensuring a predetermined initial state when the supply voltage has been applied
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
17
Electronic switching or gating, i.e. not by contact-making and -breaking
51
characterised by the use of specified components
78
by the use, as active elements, of opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
795
controlling bipolar transistors
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
21
Details of pulse counters or frequency dividers
38
Starting, stopping, or resetting the counter
Applicants:
Inventors:
Priority Data:
null30.12.1899null
Title (EN) LEVEL SENSITIVE RESET CIRCUIT FOR DIGITAL LOGIC
(FR) CIRCUIT DE REMISE A ZERO SENSIBLE A DES NIVEAUX POUR UN CIRCUIT LOGIQUE NUMERIQUE
Abstract:
(EN) A circuit for resetting a digital logic circuit, such as a digital counter. A switch (16) provides a first signal when a predetermined condition has occurred. A flip-flop (24) provides an output reset signal when the flip-flop is in a first state, in response to the first signal. The digital logic circuit to be reset (32) is coupled to the output of the flip-flop (24) for receiving its output reset signal. Feedback means (34), (36), (38) are coupled from the digital logic circuit (32) back to the flip-flop (24) for providing a signal to put the flip-flop into its other state whereby its output reset signal is terminated.
(FR) Un circuit permet d'effectuer la remise à zéro d'un circuit logique numérique tel qu'un compteur numérique. Un commutateur (16) fournit un premier signal lorsque une condition prédeterminée est établie. Une bascule (24) produit un signal de sortie de remise à zéro lorsque la bascule se trouve dans une premier état en réponse au premier signal. Le circuit logique numérique devant être remis à zéro (32) est couplé à la sortie de la bascule (24) pour recevoir son signal de sortie de remise à zero. Des moyens de réaction (34, 36, 38) sont couplés entre le circuit logique numérique (32) et la bascule (24) dans le but de produire un signal plaçant la bascule dans un autre état dans le but de mettre fin à son signal de sortie de remise à zéro.
Designated States:
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0112354AU1983016052