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1. WO1983003502 - UP/DOWN COUNTER CONTROL CIRCUIT

Publication Number WO/1983/003502
Publication Date 13.10.1983
International Application No. PCT/JP1983/000093
International Filing Date 28.03.1983
IPC
H03J 5/02 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
JTUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
5Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
02with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
H03K 21/02 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
21Details of pulse counters or frequency dividers
02Input circuits
H03K 23/66 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
23Pulse counters comprising counting chains; Frequency dividers comprising counting chains
64with a base or radix other than a power of two
66with a variable counting base, e.g. by presetting or by adding or suppressing pulses
H03K 23/86 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
23Pulse counters comprising counting chains; Frequency dividers comprising counting chains
86reversible
CPC
H03J 5/0281
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
JTUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
5Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
02with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
0245Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
0272the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer
0281the digital values being held in an auxiliary non erasable memory
H03K 21/02
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
21Details of pulse counters or frequency dividers
02Input circuits
H03K 23/665
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
23Pulse counters comprising counting chains; Frequency dividers comprising counting chains
64with a base or radix other than a power of two
66with a variable counting base, e.g. by presetting or by adding or suppressing pulses
665by presetting
H03K 23/86
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
23Pulse counters comprising counting chains; Frequency dividers comprising counting chains
86reversible
Applicants
  • SONY CORPORATION [JP]/[JP] (AllExceptUS)
  • YAMADA, Takaaki [JP]/[JP] (UsOnly)
Inventors
  • YAMADA, Takaaki
Agents
  • ITO, Tei
Priority Data
57/5446501.04.1982JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) UP/DOWN COUNTER CONTROL CIRCUIT
(FR) CIRCUIT DE COMMANDE DE COMPTEUR A INCREMENT/DECREMENT
Abstract
(EN) The design of a system is simplified by making control lines from a microprocessor as small as possible when the frequency-dividing ratio of a programmable divider of a phase-locked loop is controlled by an up/down counter. This circuit has timing control means supplied with a latch signal, data, and a clock signal; data storage means; and an up/down counter. In an up/down counter control circuit, a first level (0 or 1) of the latch signal is detected in a data loading mode based on the control of the timing control means, the data is loaded into the data storage means in synchronism with the clock signal, a second level (1 or 0) of the latch signal is detected in the up/down mode, and the content of the counter is altered in response to the level of the data synchronized with the clock signal.
(FR) La conception d'un système est simplifiée en rendant les lignes de commande provenant d'un microprocesseur aussi petites que possible lorsque le rapport de division de fréquence d'un diviseur programmable d'une boucle d'asservissement de phase est commandé par un compteur à incrément/décrément. Ce circuit possède un organe de commande de sychronisation recevant un signal de verrouillage, des données et un signal d'horloge; le circuit comprend en outre des organes de stockage de données et un compteur à incrément/décrément. Dans un circuit de commande de compteur à incrément/décrément, un premier niveau (0 ou 1) du signal de verrouillage est détecté dans un mode de chargement de données se basant sur la commande de l'organe de commande de synchronisation, les données sont chargées dans l'organe de stockage de données en synchronisme avec le signal d'horloge, un deuxième niveau (1 ou 0) du signal de verrouillage est détecté dans le mode à incrément/décrément, et le contenu du compteur est modifié en réponse au niveau des données synchronisées avec le signal d'horloge.
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