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Machine translation
1. (WO1982000394) SYNCHRONIZING CIRCUIT ADAPTABLE FOR VARIOUS TV STANDARDS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1982/000394    International Application No.:    PCT/US1981/000958
Publication Date: 04.02.1982 International Filing Date: 15.07.1981
IPC:
H04N 5/067 (2006.01)
Applicants: RCA CORPORATION
Inventors:
Priority Data:
169680 17.07.1980 US
Title (EN) SYNCHRONIZING CIRCUIT ADAPTABLE FOR VARIOUS TV STANDARDS
(FR) CIRCUIT DE SYNCHRONISATION ADAPTABLE A DIFFERENTS SYSTEMES DE LIGNES TV
Abstract: front page image
(EN)A television sync signal generator adapted for ready conversion among various television standards includes a memory (216) in which information related to the magnitude of at least one component of a composite sync signal is stored at address locations each corresponding to at least one particular time in each recurrent television frame. A clock signal generator (212) addresses the memory (216) to sequentially read out the information so the sync signal can be reconstructed. By dividing the sync signal into four intervals which are selected by paging signals from one counter, a reduction in required memory capacity is achieved. For further reducing the number of memory addresses required, each memory address contains information relating to the instantaneous resolution or clock rate. A sample rate controller (820) is coupled to the memory for having the instantaneous clock address rate controlled in response to the contents of the memory.
(FR)Un generateur de signaux de synchronisation de television concu pour la conversion de nombres differents de lignes de television comprend une memoire (216) dans laquelle l'information concernant l'intensite d'au moins un composant d'un signal de synchronisation composite est emmagasine a des adresses de memoire, chacune d'elles correspondant a au moins un moment particulier de chaque image de television recurrente. Un generateur de signaux d'horloge (212) adresse la memoire (216) pour sortir sequentiellement l'information pour que le signal de synchronisation puisse etre reconstruit. En divisant le signal de synchronisation en quatre intervalles qui sont selectionnes par des signaux de recherche provenant d'un compteur, on obtient une reduction de la capacite requise de la memoire. Pour reduire encore le nombre d'adresses de memoire requises, chaque adresse de memoire contient une information concernant la resolution instantanee ou la vitesse d'horloge. Un controleur de vitesse d'echantillon (820) est couple a la memoire pour que la vitesse d'adresse d'horloge instantanee soit commandee en reponse au contenu de la memoire.
Designated States:
Publication Language: English (EN)
Filing Language: English (EN)