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Machine translation
1. (WO1981003573) DECODER CIRCUIT FOR SEMICONDUCTOR MEMORY
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1981/003573    International Application No.:    PCT/US1980/000670
Publication Date: 10.12.1981 International Filing Date: 02.06.1980
IPC:
G11C 11/418 (2006.01), G11C 8/10 (2006.01)
Applicants:
Inventors:
Priority Data:
US80/00670 02.06.1980 WO
Title (EN) DECODER CIRCUIT FOR SEMICONDUCTOR MEMORY
(FR) CIRCUIT DECODEUR POUR MEMOIRE A SEMI-CONDUCTEUR
Abstract: front page image
(EN)A decoder circuit (66) includes a plurality of input transistors (78-86) connected to address lines (68-76). The drain terminals of the input transistors (78-86) are connected to a first power terminal and the source terminals thereof are connected to a first node (92) which is charged to low voltage state upon receipt of a precharge signal at a transistor (94). An address enable signal (58) operates a transistor (96) to connect node (92) to node (98) during receipt of the address. A node (102) is charged to a high state by operation of a transistor (100) in response to a precharge signal (56). Node (102) is discharged through a transistor (104) when a high voltage state is present at the node (98). An enable clock signal (52) is transmitted through a transistor (106) to a row line (108) when a high voltage state is present on node (102).
(FR)Un circuit decodeur (66) comprend une pluralite de transistors d"entree (178-86) connectes a des lignes d"adresse (68-76). Les bornes de drainage des transistors d"entree (78-86) sont connectees a un premier terminal de puissance et ses bornes de source sont connectees a un premier noeud (92) qui est charge a un etat de basse tension lors de la reception d"un signal de precharge par un transistor (94). Un signal de validation d"adresses (58) agit sur un transistor (96) pour connecter le noeud (92) au noeud (98) pendant la reception de l"adresse. Un noeud (102) est charge a un etat de haute tension par le fonctionnement d"un transistor (100) en reponse a un signal de precharge (56). Le noeud (102) est decharge par l"intermediaire d"un transistor (104) lorsqu"un etat haute tension est present au niveau du noeud (98). Un signal d"horloge de validation (52) est transmis par l"intermediaire d"un transistor (106) vers une ligne de rangee (108) lorsque un etat haute tension est present sur le noeud (102).
Designated States:
Publication Language: English (EN)
Filing Language: English (EN)