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Pub. No.:    WO/1981/002821    International Application No.:    PCT/JP1980/000049
Publication Date: 01.10.1981 International Filing Date: 26.03.1980
H03K 19/003 (2006.01)
Priority Data:
JP80/00049 26.03.1980 WO
Abstract: front page image
(EN)A design technique for improving reliability in functions of a gate in which technique a plurality of conventional logic circuits (gates) are used so as to give redundancy to a logic circuit itself. The new gate with redundancy is designated by the name of a fault tolerant gate. Concretely methods of forming the gate are disclosed in the cases of AND, OR, NOT, NAND, NOR and Exclusive OR gates as typical basic logic circuits, and the improvements in reliability of such gates are discussed in comparison with the conventional gates. The fault tolerant gate has a recovery function with respect to a wider variety of faults in comparison with the majority of decision circuits already commonly available. Furthermore, the disclosure shows the degree of improvement in reliability in cases where the proposed fault tolerant gate is applied to a full adder, an arithmetic logical operator and a memory, and it also discusses the reliability of a large scale logic circuit using the fault tolerant gate, and suggests that a computer with super-high reliability can be available. Thus, it is shown that the disclosed design techniques for high reliability may be greatly effective for not only improvements in reliability of logic circuits, but also improvements in yields in the manufacturing of large-scale integrated elements.
(FR)Procede d"amelioration de la fiabilite des fonctions d"une porte utilisant une pluralite de circuits logiques conventionnels (portes) de maniere a rendre un circuit logique redondant. La nouvelle porte avec redondance est appelee porte de tolerance d"erreurs. Des procedes de formation de la porte sont decrits pour des portes ET, OU, NON, NON-ET, NON-OU et OU Exclusif comme circuits logiques de base conventionnels, et des ameliorations de fiabilite de telles portes sont decrits en comparaison aux portes conventionnelles. La porte de tolerance d"erreurs possede une fonction de recuperation par rapport a une plus grande variete d"erreurs en comparaison a la majorite des circuits de decision actuellement disponibles. De plus, l"invention illustre le degre d"amelioration de fiabilite dans les cas ou la porte de tolerance d"erreurs proposee est appliquee a un additionneur entier, un operateur logique arithmetique et a une memoire, et fait egalement etat de la fiabilite d"un circuit logique a grande echelle utilisant la porte de tolerance d"erreurs, et propose la mise au point d"un ordinateur ayant une super grande fiabilite. Ainsi, il est demontre que les techniques decrites de grande fiabilite peuvent etre extremement efficaces non seulement pour les ameliorations de fiabilite des circuits logiques, mais aussi pour les ameliorations dans les domaines de fabrication d"elements integres a grande echelle.
Designated States:
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)