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Machine translation
1. (WO1981002360) BLOCK REDUNDANCY FOR MEMORY ARRAY
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1981/002360    International Application No.:    PCT/US1980/000653
Publication Date: 20.08.1981 International Filing Date: 22.05.1980
IPC:
G11C 29/00 (2006.01)
Applicants:
Inventors:
Priority Data:
120929 12.02.1980 US
Title (EN) BLOCK REDUNDANCY FOR MEMORY ARRAY
(FR) REDONDANCE DE BLOC POUR RESEAU DE MEMOIRE
Abstract: front page image
(EN)Block redundancy is utilized to improve yield and lower die cost for an electrically programmable read only memory (EPROM). The EPROM is organized 8Kx8 with four primary memory blocks (12A, 12B, 12C, 12D) on each side of a central row decoder. Each block includes an array (M) of memory cells, column select (CS), solumn decode (CD), sense amp (SA), data buffer (DB) and other overhead circuitry. One block of redundant circuitry (12RB - 1) is also provided for each set of four blocks and includes a redundant memory matrix (RM), a redundant column decoder (RCD), a redundant column select (RCS), a redundant sense amp (RSA) and a redundant data buffer (RDB). Incorporated with each primary memory block is a multiplex logic circuit (MUX) which is independently programmable to selectively disconnect the associated primary memory block and substitute the redundant memory block, including the redundant column decoder, column select, sense amp and data buffer. Each multiplex logic circuit (26) includes a polysilicon fuse (30) which is permanently programmable from a closed to an open circuit condition by applying a high voltage to the external data bit terminal (P1) which corresponds with the detective memory block cells.
(FR)Une redondance de bloc est utilisee pour ameliorer le rendement et diminuer le cout de production d"une memoire morte programmable electriquement (EPROM). L"EPROM est organisee en 8Kx8 avec quatre blocs de memoire principaux (12A, 12B, 12C, 12D) a chaque cote d"un decodeur de rangee centrale. Chaque bloc comprend un reseau (M) de cellules de memoire, un circuit de selection de colonne (CS), un circuit de decodage de colonne (CD), un amplificateur de detection (SA), un tampon de donnees (DB) et d"autres circuits. Un bloc de circuit redondant (12RB-1) est aussi prevu pour chaque groupe de quatre blocs et comprend une matrice de memoire redondante (RM), un decodeur de colonne redondant (RCD), un circuit de selection de colonne redondant (RCS), un circuit de selection de colonne redondant (RCS), un amplificateur de detection redondantes (RSA) et un tampon de donnees redondantes (RDB). Incorpore dans chaque bloc de memoire principale se trouve un circuit logique de multiplexage (MUX) qui est independamment programmable pour deconnecter de maniere selective le bloc de memoire principal associe substituer le bloc de memoire redondante, y compris le decodeur de colonne redondante, le circuit de selection de colonne redondante, l"amplificateur de detection redondant et le tampon de donnees redondantes. Chaque circuit logique de multiplexage (26) comprend un fusible en polysilicium (30) qui est programmable de maniere permanente d"une condition de circuit a une condition de circuit ouvert en appliquant une tension elevee au terminal de bit de donnees exterieure (P1) correspondant aux cellules de bloc de memoire defectueuse.
Designated States:
Publication Language: English (EN)
Filing Language: English (EN)