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Machine translation
1. (WO1981002358) TIMING OF ACTIVE PULLUP FOR DYNAMIC SEMICONDUCTOR MEMORY
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1981/002358    International Application No.:    PCT/US1980/000506
Publication Date: 20.08.1981 International Filing Date: 05.05.1980
IPC:
G11C 11/4094 (2006.01)
Applicants:
Inventors:
Priority Data:
119292 06.02.1980 US
Title (EN) TIMING OF ACTIVE PULLUP FOR DYNAMIC SEMICONDUCTOR MEMORY
(FR) SYNCHRONISATION DE L"EXTRACTION ACTIVE POUR MEMOIRE A SEMI-CONDUCTEUR DYNAMIQUE
Abstract: front page image
(EN)A method for operating a dynamic semiconductor memory circuit (10) having a memory cell (12) which comprises an access transistor (12a) connected to a half digit line (18) and a storage capacitor (12b). Each of the half digit lines (18, 22, 60 and 62) is charged or discharged as a result of either read operations carried out with the corresponding memory cells or write operations receiving incoming data states through input/output lines (42, 46). The charged state of the half digit line (18, 22, 60 and 62) is at a voltage substantially below that of the supply voltage of the circuit (10). After the half digit lines (18, 22, 60 and 62) are sensed and/or written to the desired states, a pull up circuit (48) for each of the half digit lines with voltages above a predetermined threshold to the full supply voltage. A work line signal (72) couples the charge storage capacitor (12b) to the corresponding half digit line (18) to transfer the full supply voltage of the circuit (10) into the storage capacitor (12b).
(FR)Procede de fonctionnement d"un circuit a memoire a semi-conducteur dynamique (10) ayant une cellule de memoire (12) qui comprend un transistor d"acces (12a) connecte a une ligne demi-chiffre (18) et un condensateur de stockage (12b). Chacune des lignes demi-chiffre (18, 22, 60, 62) est chargee ou dechargee comme resultat d"operations de lecture effectuees avec les cellules de memoire correspondantes ou d"operations d"ecriture recevant des etats de donnees arrivant par l"intermediaire de lignes d"entree/sortie (42, 46). L"etat charge de la ligne demi-chiffre (18, 22, 60 et 62) est a une tension sensiblement inferieure a la tension d"alimentation du circuit (10). Une fois les lignes demi-chiffre (18, 22, 60 et 62) detectees et/ou ecrites aux etats desires, un circuit d"extraction (48) pour chacune des lignes demi-chiffre (18, 22, 60 et 62) charge les lignes demi-chiffre avec des tensions superieures a un seuil predetermine de la tension d"alimentation totale. Un signal de ligne de mots (72) couple le condensateur de stockage (12b) a la ligne correspondante demi-chiffre (18) pour transferer la tension d"alimentation totale du circuit (10) dans le condensateur de stockage (12b).
Designated States:
Publication Language: English (EN)
Filing Language: English (EN)