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Machine translation
1. (WO1981002348) BANDGAP VOLTAGE REFERENCE EMPLOYING SUB-SURFACE CURRENT USING A STANDARD CMOS PROCESS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1981/002348    International Application No.:    PCT/US1980/000650
Publication Date: 20.08.1981 International Filing Date: 22.05.1980
IPC:
G05F 3/30 (2006.01)
Applicants:
Inventors:
Priority Data:
119539 07.02.1980 US
Title (EN) BANDGAP VOLTAGE REFERENCE EMPLOYING SUB-SURFACE CURRENT USING A STANDARD CMOS PROCESS
(FR) CIRCUIT DE REFERENCE DE TENSION D"ESPACE INTER-BANDES UTILISANT DES COURANTS DE SOUS-SURFACE ET UN PROCEDE STANDARD A CMOS
Abstract: front page image
(EN)A bandgap voltage reference employing only subsurface currents which may be fabricated using a standard CMOS process. The reference includes first and second vertical bipolar transistors (10, 12) having common collectors formed in an integrated circuit substrate. A first resistor (16) connects the emitter of the first transistor (10) to ground potential (20). A second resistor (22) connects the emitter of the second transistor (12) to a reference node (24) while a third resistor (26) connects the reference node to ground. A differential amplifier (28) has a positive input connected to the reference node (24), a negative input connected to the first transistor emitter and an output (30) connected to the bases of the first and second transistors and also providing the reference voltage output. In a preferred form the output of the differential amplifier is buffered by a third transistor (32) and coupled by a resistive divider (36, 38) to the first and second transistor bases so that the reference voltage may be selected at any scalar of the basic bandgap voltage.
(FR)Circuit de reference de tension d"espace utilisant seulement des courants inter-bandes de sous-surfaces pouvant etre fabrique par un procede standard a CMOS. Le circuit de reference comprend un premier et un deuxieme transistor bi-polaire vertical (10, 12) dont les collecteurs communs sont formes dans un substrat de circuit integre. Une premiere resistance (16) connecte l"emetteur du premier transistor (10) au potentiel de masse (20). Une deuxieme resistance (22) connecte l"emetteur du deuxieme transistor (12) a un noeud de reference (24) tandis qu"une troisieme resistance (26) connecte le noeud de reference a la masse. Un amplificateur differentiel (24) possede une entree positive connectee au noeud de reference (24), une entree negative connectee a l"emetteur du premier transistor et une sortie (30) connectee aux bases du premier et du deuxieme transistor et fournissant aussi la sortie de tension de reference. Dans un mode de realisation preferentiel la sortie de l"amplificateur differentiel est pourvue d"un tampon constitue par un troisieme transistor (32) et elle est couplee par un diviseur resistif (36, 38) aux bases du premier et du deuxieme transistors de sorte que la tension de reference peut etre selectionnee a n"importe quelle valeur scalaire de la tension d"espace inter-bandes.
Designated States:
Publication Language: English (EN)
Filing Language: English (EN)