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Machine translation
1. (WO1981002080) DYNAMIC RATIOLESS CIRCUITRY FOR RANDOM LOGIC APPLICATIONS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1981/002080    International Application No.:    PCT/US1980/000505
Publication Date: 23.07.1981 International Filing Date: 05.05.1980
IPC:
H03K 19/0185 (2006.01), H03K 19/096 (2006.01), H03K 23/42 (2006.01), H03K 3/356 (2006.01)
Applicants:
Inventors:
Priority Data:
111274 11.01.1980 US
Title (EN) DYNAMIC RATIOLESS CIRCUITRY FOR RANDOM LOGIC APPLICATIONS
(FR) RESEAU DE CIRCUIT DYNAMIQUE SANS RAPPORT POUR APPLICATION A LOGIQUE RANDOMISEE
Abstract: front page image
(EN)A logic circuit (20) is provided for receiving an input signal and for generating a delayed output signal being clocked by first and second non-overlapping clock phases. Logic circuit (20) includes a voltage supply (V). A precharge transistor (30) is interconnected to the voltage supply (V) and is clocked by the first clock phase. A discharge transistor (32) is interconnected to the precharge transistor (30) thereby defining a first node (A) and is clocked by the second clock phase to conditionally discharge the first node (A). An input logic circuit (34) is interconnected to the discharge transistor (32) thereby defining a second node (B) for providing a discharge path from the first node (A) to a ground voltage potential, the input logic circuit (34) is connected to receive the input signal. An output transistor (36) is interconnected to the first node (A) for generating the delayed output signal. The output transistor (36) is clocked by the second clock phase. A capacitor (38) is interconnected to the first node (A) and the output transistor (36) and is clocked by the second clock phase for maintaining the first node (A) at a predetermined voltage level by a bootstrapping operation.
(FR)Un circuit dynamique (20) sert a recevoir un signal d"entree et a produire un signal de sortie retarde synchronise par des premiere et seconde phases d"horloge non chevauchantes. Le circuit logique (20) comprend un alimentation de tension (V). Un transistor de precharge (30) est interconnecte a l"alimentation de tension (V) et est synchronise par la premiere phase d"horloge. Un transistor de decharge (32) est interconnecte au transistor de precharge (30) definissant ainsi un premier noeud (A) et est synchronise par la seconde phase d"horloge pour decharger de maniere conditionnelle le premier noeud (A). Un circuit logique d"entree (34) est interconnecte au transistor de decharge (32) definissant ainsi un second noeud (V) pour produire un chemin de decharge depuis le premier noeud (A) vers un potentiel de tension de masse, le circuit logique d"entree (34) etant connecte pour recevoir le signal d"entree. Un transistor de sortie (36) est interconnecte sur le premier noeud (A) pour generer le signal de sortie retarde. Le transistor de sortie (36) est synchronise par la seconde phase d"horloge. Un condensateur (38) est interconnecte sur le premier noeud (A) et le transistor de sortie (36) et est synchronise par la seconde phase d"horloge pour maintenir le premier noeud (A) a un niveau de tension predetermine par une operation d"introduction d"une sequence d"appel.
Designated States:
Publication Language: English (EN)
Filing Language: English (EN)