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Machine translation
1. (WO1981000928) SAMPLE AND HOLD CIRCUIT WITH OFFSET CANCELLATION
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1981/000928    International Application No.:    PCT/US1980/001130
Publication Date: 02.04.1981 International Filing Date: 02.09.1980
IPC:
G11C 27/02 (2006.01)
Applicants:
Inventors:
Priority Data:
79339 27.09.1979 US
Title (EN) SAMPLE AND HOLD CIRCUIT WITH OFFSET CANCELLATION
(FR) CIRCUIT ECHANTILLONNEUR-BLOQUEUR AVEC ANNULATION DU DECALAGE
Abstract: front page image
(EN)An operational amplifier based sample and hold circuit adapted for implementation as an integrated circuit is comprised of MOS transistor elements. The operational amplifier (11) has a positive terminal (+) connected to ground and a negative input lead connected to one side of a capacitor (20), the other side of which is connected to a first MOS transistor (18) whose gate is controlled by clock signals (V1). A feedback lead (22) from the operational amplifier output (16) is connected to second (24) and third (26) transistors in parallel The second transistor (24) is connected to the input lead between the capacitor and the operational amplifier and the third transistor (26) is connected to the input lead between the capacitor and the first transistor. The gates of the second and third transistors are connected to separate clock signal sources (V3, V2). The timing of the clock signals to the three transistors is such that the Vin signal is sampled and held and the operational amplifier's offset is cancelled.
(FR)Circuit echantillonneur-bloqueur utilisant un amplificateur operationnel adapte pour la mise en application en tant que circuit integre comprenant des elements de transistor MOS. L'amplificateur operationnel (11) possede un terminal positif (+) connecte a la masse et un fil negatif d'entree connecte a une extremite d'un condensateur (20), l'autre extremite duquel est connectee a un premier transistor MOS (18) dont la porte est commandee par des signaux d'horloge (V1). Un fil de retroaction (22) venant de la sortie (16) de l'amplificateur operationnel est connecte en parallele au deuxieme (24) et au troisieme (26) transistors. Le deuxieme transistor (24) est connecte au fil d'entree entre le condensateur et l'amplificateur operationnels et le troisieme transistor (26) est connecte au fil d'entree entre le condensateur et le premier transistor. Les portes du deuxieme et du troisieme transistors sont connectees a des sources separees (V3, V2) de signaux d'horloge. La synchronisation des signaux d'horloge aux trois transistors est telle que le signal (V) a l'entree est echantillonne et bloque et que le decalage de l'amplificateur operationnel est annule.
Designated States:
Publication Language: English (EN)
Filing Language: English (EN)