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Machine translation
1. (WO1981000167) MAGNETIC BUBBLE PACKAGE WITH CHIPS MOUNTED FACE-TO-FACE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1981/000167    International Application No.:    PCT/US1980/000746
Publication Date: 22.01.1981 International Filing Date: 19.06.1980
IPC:
G11C 19/08 (2006.01)
Applicants:
Inventors:
Priority Data:
53709 29.06.1979 US
Title (EN) MAGNETIC BUBBLE PACKAGE WITH CHIPS MOUNTED FACE-TO-FACE
(FR) UNITE A MEMOIRE A BULLES MAGNETIQUES AVEC MICROPLAQUETTES MONTEES FACE-A-FACE
Abstract: front page image
(EN)A magnetic bubble memory package comprising bubble memory chips (26A, 26B) arranged in pairs, with the propagate and functional elements for bubble manipulation, one of each pair being the mirror image of the other, and mounted on a printed circuit board assembly (30A, 30B) face-to-face and surrounded by spaced orthogonally oriented drive coils (22, 24) and bias magnets (14, 16) for the support and propagation of the bubbles. Each chip of each pair may be connected in series and in parallel by the printed circuit board assembly so that individual chips or a series of chips can be selectively accessed. Two embodiments of interconnections between such circuit boards are disclosed to meet the series and parallel connection requirements for the package selected.
(FR)Unite a memoire a bulles magnetiques comprenant des microplaquettes de memoire a bulles (26A, 26B) disposees en paires, avec les elements de propagation et fonctionnels de manipulation des bulles, l"une des deux plaquettes de chaque paire etant l"image de miroir de l"autre, les microplaquettes etant montees sur une plaque a circuits imprimes (30A, 30B) en face-a-face et entourees d"enroulements d"entrainement espaces et orientes orthogonalement (22, 24), et des aimants de polarisation (14, 16) de support et de propagation des bulles. Chaque plaquette de chaque paire peut etre connectee en serie et en parallele par la plaque a circuits imprimes de maniere a ce qu"il soit possible d"avoir acces selectivement a des plaquettes individuelles ou a une serie de plaquettes. Deux modes de realisation d"interconnexion entre de telles plaques de circuits sont decrits pour satisfaire les conditions de connexion en serie et en parallele de l"unite de memoire selectionnee.
Designated States:
Publication Language: English (EN)
Filing Language: English (EN)