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Machine translation
1. (WO1980002880) INTEGRATED CIRCUIT HAVING FREQUENCY DIVIDER CIRCUIT ADAPTABLE FOR HIGH-SPEED TESTING
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1980/002880    International Application No.:    PCT/JP1980/000138
Publication Date: 24.12.1980 International Filing Date: 19.06.1980
IPC:
H03K 21/40 (2006.01), G04D 7/12 (2006.01), G04G 99/00 (2010.01)
Applicants:
Inventors:
Priority Data:
79/77169 19.06.1979 JP
Title (EN) INTEGRATED CIRCUIT HAVING FREQUENCY DIVIDER CIRCUIT ADAPTABLE FOR HIGH-SPEED TESTING
(FR) CIRCUIT INTEGRE AYANT UN CIRCUIT DIVISEUR DE FREQUENCE ADAPTABLE AUX ESSAIS RAPIDES
Abstract: front page image
(EN)An integrated circuit having a frequency divider circuit adaptable for high-speed testing. The frequency divider circuit is split into two stages of a pre-stage frequency divider circuit (12) and a post-stage frequency divider circuit (14). An output buffer circuit (3) and a testing signal-input circuit (4) are connected in parallel to an alarm terminal (7). The testing signal applied to the alarm terminal (7) is fed to the poststage frequency divider circuit (14) through the testing signal-input circuit (4) and a switching circuit (13).
(FR)Le circuit diviseur de frequence comprend deux etapes d"un circuit diviseur de frequence de pre-etage (12) et d"un circuit diviseur de frequence de poste-etage (14). Un circuit tampon de sortie (3) et un circuit d"entree de signaux d"essais (4) sont connectes en parallele a une borne d"alarme (7). Le signal d"essai applique a la borne d"alarme (7) est envoye au circuit diviseur de frequence de poste-etage (14) par l"intermediaire du circuit d"entree de signaux d"essais (4) et d"un circuit de commutation (13).
Designated States:
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)