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Machine translation
1. (WO1980001528) TRI-STATE LOGIC BUFFER CIRCUIT
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1980/001528    International Application No.:    PCT/US1980/000002
Publication Date: 24.07.1980 International Filing Date: 02.01.1980
IPC:
H03K 19/094 (2006.01)
Applicants:
Inventors:
Priority Data:
2741 11.01.1979 US
Title (EN) TRI-STATE LOGIC BUFFER CIRCUIT
(FR) CIRCUIT LOGIQUE TAMPON A TROIS ETATS
Abstract: front page image
(EN)A first MOS (metal-oxide-semiconductor) NOR-gate device feeding a second MOS NOR-gate device feeding an MOS output load device is arranged to yield a three output level buffer circuit, that is, a circuit whose output to a common data bus line can be "high" ("1"), "low" ("0"), or of very high impedance ("floating"). Each NOR-gate contains a low ("load") depletion mode MOS transistors (M3, M5) and a high ("driver") enhancement mode (M4, M"4, M6, M"6) MOS; the output load device contains an output driver enhancement mode MOS transistor (M2) and an output load MOS transistor (M1) having a threshold intermediate that of the depletion mode and enhancement mode M0S transistors. In this manner, only a single voltage source VDD, of typically about +5 volts in N-MOS integrated circuit technology is required to power the buffer circuit completely.
(FR)Un premier dispositif semi-conducteur-meta-oxyde (MOS) a porte non/ou (NOR) alimentant un second dispositif (MOS) a porte (NOR) alimentant un dispositif (MOS) a charge de sortie, pour former un circuit tampon a trois niveaux de sorties, c"est-a-dire un circuit dont la sortie vers une ligne de bus de donnees communes peut etre "haute" ("1"), "basse" ("O") ou de tres haute impedance ("flottante"). Chaque porte (NOR) contient des transistors (MOS) de mode d"appauvrissement bas ("charge") (M3, M5) et un mode (MOS) d"enrichissement haut ("entrainement") (M4, M"4 M6, M"6); le dispositif de charge de sortie contient un transistor (MOS) de mode d"enrichissement d"entrainement de sortie (M2) et un transistor (MOS) de charge de sortie (M1) ayant un seuil intermediaire entre ceux des transistors (MOS) de mode d"appauvrissement et d"enrichissement. De cette maniere, une seule source de tension VDD, typiquement d"environ +5 volts, dans une technologie de circuit integre N-MOS est necessaire pour alimenter completement le circuit tampon.
Designated States:
Publication Language: English (EN)
Filing Language: English (EN)