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Machine translation
1. (WO1980000632) HIGH DENSITY MEMORY SYSTEM
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1980/000632    International Application No.:    PCT/US1979/000675
Publication Date: 03.04.1980 International Filing Date: 28.08.1979
IPC:
G06F 13/42 (2006.01), G11C 11/409 (2006.01), G11C 11/414 (2006.01), G11C 7/22 (2006.01)
Applicants:
Inventors:
Priority Data:
939297 01.09.1978 US
Title (EN) HIGH DENSITY MEMORY SYSTEM
(FR) SYSTEME DE MEMOIRE A HAUTE DENSITE
Abstract: front page image
(EN)A high density memory system includes a plurality of addressable circuit boards (201 to 202). Each board includes a pair of chip arrays (22), each chip array (22) including a plurality of memory elements (56) arranged in groups. Each memory element (56) is a charge coupled device including a plurality of storage loops. In operation, address signals on an address line (32) cause a decoder (28) associated with a selected array (22) to provide a comparison signal to clock driver means (24) including a plurality of individual clock drivers (241 to 24n), one of which is selected by row address signals thereby providing a changed clock pulse width signal which change is detected, thereby enabling a group of the memory elements (56). A function driver circuit (26) provides a mode control signal which places the enabled memory elements (56) in a read or write operational mode. A high density memory system is achieved because only a low number of electrical interconnection conductors is utilized.
(FR)Un systeme de memoire a haute densite comprend une pluralite de panneaux de circuits adressables (20l a 20n). Chaque panneau comprend une paire de rangees de microplaquettes (22), chaque rangee de microplaquettes comprenant une pluralite d"elements de memoire presentes en groupes. Chaque element de memoire (56) est un dispositif de couplage en charge comprenant une pluralite de boucles de stockage. Lors de l"actionnement des signaux d"adresse sur une ligne d"adresse (32) permettent a un decodeur (28) associe avec une rangee selectionnee (22) de fournir un signal de comparaison a un moyen d"horloge excitatrice (24) comprenant une pluralite d"horloges excitatrices individuelles, l"une d"entre elles etant selectionnee par des signaux de rang d"adresse fournissant ainsi une largeur de signal d"impulsion d"horloge changee, lequel changement est decele, validant ainsi un groupe d"elements de memoire (56). Un circuit excitateur de fonction (26) fournit un signal de modalite de commandement qui place les elements de memoire (56) valides en un mode operationnel de lecture ou d"ecriture. Un systeme de memoire a haute densite est obtenu seulement parce qu"un nombre restreint de conducteurs d"interconnexion electrique est utilise.
Designated States:
Publication Language: English (EN)
Filing Language: English (EN)