WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO1980000387) DATA STORAGE SYSTEM
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1980/000387    International Application No.:    PCT/US1979/000565
Publication Date: 06.03.1980 International Filing Date: 31.07.1979
IPC:
G11C 19/28 (2006.01)
Applicants:
Inventors:
Priority Data:
930613 03.08.1978 US
Title (EN) DATA STORAGE SYSTEM
(FR) SYSTEME DE MEMOIRE DE DONNEES
Abstract: front page image
(EN)A data storage system (10) includes a charge coupled device shift register (12) and a detection circuit (20) for detecting the binary value represented by the charge level or signal within each cell location of the shift register. The detection circuit (20) includes a sense amplifier (30) for comparing the signals from two adjacent cell locations (b0, b1), with one signal representing a known binary value. The comparison of adjacent cell locations compensates for signal losses during shifting, since the losses experienced by adjacent cell locations are nearly identical. Switching transistors (40, 42) cause an adjustment voltage (Va) to be added to one of the signals prior to comparison. The output of the sense amplifier is provided to a flip-flop (32), which controls the switching transistors and is set to a predetermined state whenever a reference data item is located in the cell location (b0) providing the signal representing the known binary value.
(FR)Un systeme de memoire de donnees (10) comprend un registre a decalage a dispositif d"accouplement de charge (12) et un circuit de detection (20) pour detecter la valeur binaire representee par le niveau ou signal de charge dans chaque adresse de cellule du registre a decalage. Le circuit de detection (20) comprend un amplificateur de detection (30) pour comparer les signaux provenant de deux adresses de cellules adjacentes (b0, b1), un signal representant une valeur binaire connue. La comparaison des adresses de cellules adjacentes compense les pertes de signaux pendant le decalage, etant donne que les pertes subies par les adresses de cellules adjacentes sont presque identiques. Des transistors de commutation (30, 42) produisent une tension d"ajustement qui est ajoutee a l"un des signaux avant comparaison. La sortie de l"amplificateur de detection est transmise a une bascule (32) qui commande les transistors de commutation et est forcee de prendre une position predeterminee a chaque fois qu"une donnee elementaire de reference est localisee dans l"adresse de cellules (b0) produisant le signal representant la valeur binaire connue.
Designated States:
Publication Language: English (EN)
Filing Language: English (EN)