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1. WO1979000914 - MEMORY DEVICE

Publication Number WO/1979/000914
Publication Date 15.11.1979
International Application No. PCT/US1979/000178
International Filing Date 19.03.1979
IPC
G06F 13/42 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
42Bus transfer protocol, e.g. handshake; Synchronisation
G11C 19/28 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
19Digital stores in which the information is moved stepwise, e.g. shift registers
28using semiconductor elements
G11C 5/00 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
G11C 5/06 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
H03K 17/30 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
17Electronic switching or gating, i.e. not by contact-making and -breaking
30Modifications for providing a predetermined threshold before switching
CPC
G06F 13/4243
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
42Bus transfer protocol, e.g. handshake; Synchronisation
4204on a parallel bus
4234being a memory bus
4243with synchronous protocol
G11C 19/282
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
19Digital stores in which the information is moved stepwise, e.g. shift register
28using semiconductor elements
282with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
G11C 19/287
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
19Digital stores in which the information is moved stepwise, e.g. shift register
28using semiconductor elements
287Organisation of a multiplicity of shift registers
G11C 5/00
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
G11C 5/066
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
066Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
H03K 17/302
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
17Electronic switching or gating, i.e. not by contact-making and –breaking
30Modifications for providing a predetermined threshold before switching
302in field-effect transistor switches
Applicants
Inventors
Priority Data
89532811.04.1978US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MEMORY DEVICE
(FR) DISPOSITIF DE MEMOIRE
Abstract
(EN)
A memory device (10) includes a circuit for reducing the number of pins or external terminals on the memory device (10). A threshold detector (49) within the circuit detects the difference in voltage between signals applied at two external pins (C0, F0). A clocking signal at one pin (C0) provides, in addition to a synchronizing function, a memory device select function, and a signal at the other pin (F0) provides memory mode select as well as memory address, data input and data output functions. Switching transistors (24, 28) controlled by the output of the threshold detector (40) connect the external pins (C0, F0) to the power and ground terminals of an internal power supply (16) so that the signals at the two external pins (C0, F0) also provide the power and ground signals to the memory device (10).
(FR)
Une dispositif de memoire (10) comprend un circuit pour reduire le nombre de broches ou bornes externes sur le dispositif de memoire (10). Un detecteur de seuil (40) inclus dans le circuit detecte la difference de tension entre les signaux appliques a deux broches externes (C0, F0). Un signal d"horloge en une broche (C0) exerce, en plus d"une fonction de synchronisation, une fonction de selection du dispositif de memoire, et un signal a l"autre broche (F0) exerce des fonctions de selection du mode de la memoire et adresse de memoire, ainsi que la sortie et l"entree des donnees. Des transistors de commutation (24, 28) commandes par la sortie du detecteur de seuil (40) connectent les broches externes (C0, F0) aux bornes de puissance et de terre d"une alimentation de puissance interne (16) de sorte que les signaux aux broches externes (C0, F0) produisent aussi les signaux de puissance et de terre au dispositif de memoire (10).
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