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Machine translation
1. (WO1979000564) DELAY CIRCUIT
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1979/000564    International Application No.:    PCT/JP1979/000023
Publication Date: 23.08.1979 International Filing Date: 30.01.1979
IPC:
H03J 7/26 (2006.01), H03K 5/135 (2006.01)
Applicants:
Inventors:
Priority Data:
78/9962 30.01.1978 JP
Title (EN) DELAY CIRCUIT
(FR) CIRCUIT A RETARD
Abstract: front page image
(EN)A delay circuit comprising counter circuits (32, 34), a flip-flop circuit (36), circuits (30, 40) for holding the flip-flop circuit in its reset situation for the duration of first signals (Xo, Yo) and a gate circuit (38) receiving a second signal (Sd) and operated by the output of the flip-flop circuit (36). According to this delay circuit, a relatively large delay may be easily accomplished in a digital Manner during the period up to the stoppage of output of a second signal after the termination of the first signal, even by the use of integrated circuits. This is adapted to be used for the tuning circuit for electronic-tuning type radio receivers.
(FR)Circuit a retard comprenant des circuits compteurs (32, 34), un circuit a bascule (36), des circuits (30, 40) de maintien du circuit a bascule dans sa position de mise a zero pendant la duree des premiers signaux (Xo, Yo) et un circuit portillon (38) recevant un second signal (Sd) et qui fonctionne par la sortie du circuit a bascule (36). Avec ce circuit a retard, on peut obtenir numeriquement un retard relativement grand pendant la periode allant de la fin du premier signal jusqu"a l"arret de la sortie du second signal, meme en utilisant des circuits integres. Ceci s"adapte au circuit de synthonisation de recepteurs radio a synthonisation electronique.
Designated States:
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)