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Machine translation
1. (WO1979000461) COMPLEMENTARY MIS-SEMICONDUCTOR INTEGRATED CIRCUITS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1979/000461    International Application No.:    PCT/JP1978/000048
Publication Date: 26.07.1979 International Filing Date: 11.12.1978
IPC:
G11C 11/412 (2006.01), G11C 11/417 (2006.01), G11C 11/418 (2006.01), G11C 5/06 (2006.01), H01L 27/118 (2006.01), H03K 3/356 (2006.01)
Applicants:
Inventors:
Priority Data:
77/158445 30.12.1977 JP
Title (EN) COMPLEMENTARY MIS-SEMICONDUCTOR INTEGRATED CIRCUITS
(FR) CIRCUITS INTEGRES A SEMI-CONDUCTEURS MIS COMPLEMENTAIRES
Abstract: front page image
(EN)A semiconductor device having a plurality of unit cells, wherein the unit cells arranged along the row direction of a semiconductor substrate define unit cell arrays which are arranged along a columnar direction of the semiconductor substrate, and include depletion regions formed between adjacent primitive cell arrays. The unit cells are each composed of first and second P-channel MIS-transistors and first and second N-channel MIS-transistors. The first P-channel MIS-transistor and first N-channel MIS-transistor each have a gate defining a first single common gate, and the second P-channel MIS-transistor and second N-channel MIS-transistor each have a gate defining a second single common gate. The sources or drains of the first and second P-channel MIS-transistors each form a first single common source or drain and, on the other hand, the sources or drains of the first and second N-channel MIS-transistors each form a second single common source or drain. The first and second single common gates are each provided at both terminals of the unit cell arrays with terminal electrodes and are further provided at the center of the unit cell arrays with central terminal electrodes. The unit cells include small depletion regions extending along both sides of the unit cell arrays. These small depletion regions may be used as regions for wiring along the columnar direction of the small depletion regions.
(FR)Dispositif a semi-conducteur comprenant une pluralite de cellules unitaires, dans lequel les cellules unitaires disposees dans le sens des rangees d"un substrat semi-conducteur definissant des rangees de cellules unitaires disposees dans le sens des colonnes d"un substrat semi-conducteur ainsi que des zones de rarefaction entre les rangees de cellules primitives. Chaque cellule unitaire est composee d"un premier et d"un second transistor MIS a canal P et d"un premier et d"un second transistor MIS a canal N. Le premier transistor MIS a canal P et le premier transistor MIS a canal N ont chacun une porte definissant une premiere porte commune unique, et le second transistor MIS a canal P ainsi que le second transistor MIS a canal N ont chacun une porte definissant une seconde porte commune unique. Les emetteurs des premier et second transistors MIS a canal p forment un premier emetteur commun et, d"autre part, les emetteurs des premier et second transistors MIS a canal N forment un second emetteur commun. Chacune des premiere et seconde portes communes est pourvue aux deux terminaux des rangees de cellules unitaires d"electrodes de borne et sont egalement munies, au centre des rangees de cellules unitaires d"electrodes centrales de borne. Les cellules unitaires comportent des petites zones de rarefaction qui s"etendent sur les deux cotes des rangees de cellules. Les zones de rarefaction peuvent etre utilisees comme zones pour le cablage dans le sens des colonnes de petites zones de rarefaction.
Designated States:
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)