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1. (US20110039509) Wireless receiver

Application Number: 12854210 Application Date: 11.08.2010
Publication Number: 20110039509 Publication Date: 17.02.2011
Grant Number: 08849226 Grant Date: 30.09.2014
Publication Kind : B2
IPC:
H04B 1/18
H04J 1/16
H04L 7/00
H04B 1/40
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
B
TRANSMISSION
1
Details of transmission systems, not covered by a single one of groups H04B3/-H04B13/123; Details of transmission systems not characterised by the medium used for transmission
06
Receivers
16
Circuits
18
Input circuits, e.g. for coupling to an aerial or a transmission line
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
J
MULTIPLEX COMMUNICATION
1
Frequency-division multiplex systems
02
Details
16
Monitoring arrangements
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7
Arrangements for synchronising receiver with transmitter
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
B
TRANSMISSION
1
Details of transmission systems, not covered by a single one of groups H04B3/-H04B13/123; Details of transmission systems not characterised by the medium used for transmission
38
Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
40
Circuits
Applicants: Bruchner Wolfgang
Cascoda Limited
Inventors: Bruchner Wolfgang
Agents: Renner, Otto, Boisselle & Sklar, LLP
Priority Data:
Title: (EN) Wireless receiver
Abstract: front page image
(EN)

A wireless receiver designed to conform to the standard IEEE 802.15.4. The receiver comprises an analog front-end and a digital decoder. The analog components of the front end include one or more amplifiers and an analog-to-digital converter (ADC). The digital decoder receives the output of the ADC and demodulates it in a demodulator which is driven at an a chip frequency by an internal or external clock. The demodulator comprises a sampler operable to sample the digital signal at a sampling frequency and a correlation unit operable to process a set of bits, referred to as a chip code, in the sampled digitized signal and output therefrom a set of correlation values. The set of correlation values is an indicator of likely mapping between the chip code that has been processed and a set of possible chip codes defined according to the standard. The demodulator further comprises a symbol selection unit and a frequency correction unit. The symbol selection unit has the function of deciding which symbol has been received based on an analysis of each set of correlation values. The frequency correction unit is operable to make adjustments to the chip frequency based on the correlation values output from the correlation unit, specifically to increase or decrease the chip frequency based on a measurement of whether the maximum correlation value among each set of correlation values occurs earlier or later than predicted. This scheme has the advantage that phase and frequency compensation is done after correlation avoiding the need for coherent demodulation while at the same time not requiring the stringent specifications of a conventional non-coherent demodulation scheme.