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1. US20100327969 - Power amplifier having parallel amplification stages and associated impedance matching networks

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[ EN ]

Claims

1. A device, comprising:
an input terminal;
an output terminal;
a driver amplifier having an input terminal, and an output terminal, where the input terminal is connected to the input terminal;
a first main amplifier having an input terminal and an output terminal, and configured to receive a first activation signal for selectively activating and deactivating the first amplifier;
a second main amplifier having an input terminal and an output terminal, and configured to receive a second activation signal for selectively activating and deactivating the second amplifier;
a control circuit configured to supply the first and second activation signals to the first and second amplifiers, respectively;
a first impedance matching circuit directly connected between the output terminal of the driver amplifier and a first intermediate node;
a second impedance matching circuit directly connected between the first intermediate node and a second intermediate node;
a third impedance matching circuit directly connected between the second intermediate node and the input terminal of the first main amplifier;
a fourth impedance matching circuit directly connected between the second intermediate node and the input terminal of the second main amplifier;
a fifth impedance matching circuit directly connected between the output terminal of the first main amplifier and a third intermediate node;
a sixth impedance matching circuit directly connected between the output terminal of the second main amplifier and the third intermediate node;
an impedance transformation network directly connected between the first intermediate node and the third intermediate node; and
a seventh impedance matching circuit directly connected between the third intermediate node and the output terminal.
2. The device of claim 1, further comprising:
a third main amplifier having an input terminal and an output terminal, and configured to receive a third activation signal for selectively activating and deactivating the third amplifier;
an eighth impedance matching circuit directly connected between the second intermediate node and the input terminal of the third main amplifier; and
a ninth impedance matching circuit directly connected between the output terminal of the third main amplifier and the third intermediate node.
3. The device of claim 1, wherein the first and second activation signals are bias signals for turning on and off the first and second main amplifiers, respectively.
4. The device of claim 1, wherein the first and second activation signals are configured in at least one operating mode to turn on both the first and second main amplifiers at a same time.
5. The device of claim 1, wherein the first and second main amplifiers are each biased to operate in class AB amplification mode.
6. A device, comprising:
an input terminal;
an output terminal;
a first impedance matching circuit directly connected between the input terminal and a first intermediate node;
a driver amplifier having an input terminal, and an output terminal, and configured to receive a driver amplifier activation signal for selectively activating and deactivating the driver amplifier;
a bypass amplifier having an input terminal, and an output terminal, and configured to receive a bypass amplifier activation signal for selectively activating and deactivating the bypass amplifier;
a second impedance matching circuit directly connected between the first intermediate node and the input node of the driver amplifier;
a third impedance matching circuit directly connected between the first intermediate node and the input node of the bypass amplifier;
a first main amplifier having an input terminal and an output terminal, and configured to receive a first activation signal for selectively activating and deactivating the first main amplifier;
a second main amplifier having an input terminal and an output terminal, and configured to receive a second activation signal for selectively activating and deactivating the second main amplifier;
a control circuit configured to supply the driver amplifier activation signal to the driver amplifier, to supply the bypass amplifier activation signal to the bypass amplifier, and to supply the first and second activation signals to the first and second main amplifiers, respectively;
a fourth impedance matching circuit directly connected between the output terminal of the driver amplifier and a second intermediate node;
a fifth impedance matching circuit directly connected between the output terminal of the bypass amplifier and the second intermediate node;
a sixth impedance matching circuit directly connected between the second intermediate node and a third intermediate node;
a seventh impedance matching circuit directly connected between the third intermediate node and the input terminal of the first main amplifier;
an eighth impedance matching circuit directly connected between the third intermediate node and the input terminal of the second main amplifier;
a ninth impedance matching circuit directly connected between the output terminal of the first main amplifier and a fourth intermediate node;
a tenth impedance matching circuit directly connected between the output terminal of the second main amplifier and the fourth intermediate node;
an impedance transformation network directly connected between the second intermediate node and the fourth intermediate node; and
an eleventh impedance matching circuit directly connected between the fourth intermediate node and the output terminal.
7. The device of claim 6, further comprising:
a third main amplifier having an input terminal and an output terminal, and configured to receive a third activation signal for selectively activating and deactivating the third amplifier;
a twelfth impedance matching circuit directly connected between the third intermediate node and the input terminal of the third main amplifier; and
a thirteenth impedance matching circuit directly connected between the output terminal of the third main amplifier and the fourth intermediate node.
8. The device of claim 6, wherein the first and second activation signals are bias signals for turning on and off the first and second main amplifiers, respectively.
9. The device of claim 6, wherein the first and second activation signals are configured in at least one operating mode to turn on both the first and second main amplifiers at a same time.
10. The device of claim 6, wherein the first and second main amplifiers are each biased to operate in class AB amplification mode.
11. The device of claim 6, wherein the driver amplifier activation signal is a bias signal for turning on and off the driver amplifier, and the bypass amplifier activation signal is a bias signal for turning on and off the bypass amplifier.
12. A device for amplifying a signal, comprising:
a driver amplifier stage including a driver amplifier and a driver amplifier output matching network;
a device output terminal matching network;
a secondary amplification stage in series between the driver amplifier stage and the device output terminal matching network, wherein the secondary amplification stage comprises,
an impedance transformation network, and
a main amplification stage in parallel with the impedance transformation network, wherein the main amplification stage includes
a plurality of main amplification branches in parallel with each other, wherein each of the main amplification branches includes a main amplifier, an input impedance matching network, and an output impedance matching network, and
a main amplification stage input matching network in series with the plurality of parallel main amplification branches; and
a control circuit configured to supply activation signals to each of the main amplification branches to selectively turn on and off the main amplification branches;
wherein the device has no switches in the path of the signal that is amplified, and
wherein in at least one operating mode, the control circuit is configured to turn on at least two of the main amplification branches at a same time.
13. The device of claim 12, wherein the plurality of main amplification branches includes at least three main amplification branches.
14. The device or claim 12, further comprising:
a bypass amplifier stage in parallel with the driver amplifier stage, the bypass amplifier stage including a bypass amplifier, a bypass amplifier input matching network, and a bypass amplifier output matching network; and
a device input terminal matching network,
wherein the driver amplifier stage further comprises a driver amplifier stage input matching network, and
wherein the device input matching network is connected to the driver amplifier stage input matching network and the bypass amplifier stage input matching network.
15. The device of claim 12, wherein the activation signals are bias signals for turning on and off the amplifiers in the main amplification branches.
16. The device of claim 12, wherein each of the main amplifiers is biased to operate in class AB amplification mode.