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1. US20070040585 - High speed, low power CMOS logic gate

Office
United States of America
Application Number 11207806
Application Date 22.08.2005
Publication Number 20070040585
Publication Date 22.02.2007
Grant Number 7285986
Grant Date 23.10.2007
Publication Kind B2
IPC
H03K 19/096
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
08using semiconductor devices
094using field-effect transistors
096Synchronous circuits, i.e. using clock signals
CPC
H03K 19/0963
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
08using semiconductor devices
094using field-effect transistors
096Synchronous circuits, i.e. using clock signals
0963using transistors of complementary type
H03K 19/0027
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
0021Modifications of threshold
0027in field effect transistor circuits
H03K 19/215
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
20characterised by logic function, e.g. AND, OR, NOR, NOT circuits
21EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
215using field-effect transistors
Applicants Micron Technology, Inc.
Inventors Lovett Simon J.
Gans Dean D.
Weber Larren G.
Agents Dickstein Shapiro LLP
Priority Data 11207806 22.08.2005 US
Title
(EN) High speed, low power CMOS logic gate
Abstract
(EN)

A logic gate with a differential evaluation stage, precharge circuitry for precharging outputs of the gate, latch circuitry for latching the outputs and an inverter. The gate uses high speed, low threshold voltage devices in the evaluation stage, yet uses higher threshold voltage devices in other portions of the gate (e.g., precharge circuitry). This use of dual threshold voltage devices minimizes power consumption while maximizing speed. During standby mode, the gate is operated in an evaluation mode to substantially mitigate standby current.