Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (US20060197129) Buried and bulk channel finFET and method of making the same
Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

Claims

1. A fin-field effect transistor, comprising:
a material stack including a non-inverting surface channel;
a fin of semiconductor material positioned on said material stack, said fin including first and second opposing side surfaces; and
a gate electrode positioned on said first and second opposing side surfaces of said fin.
2. The transistor of claim 1 wherein said channel includes at least one buried channel.
3. The transistor of claim 1 wherein said channel is a bulk channel.
4. The transistor of claim 1 wherein said fin includes a top surface, and wherein said gate electrode is positioned on said top surface.
5. The transistor of claim 1 wherein said transistor is non-inverting.
6. The transistor of claim 1 wherein said channel is operated by changing the degree of depletion.
7. The transistor of claim 1 wherein the device is self-aligned.
8. The transistor of claim 1 wherein the device is non-self-aligned.
9. The transistor of claim 1 wherein said semiconductor material is chosen from one of or a composite of Gallium, Arsenide, Aluminum, Indium, Phosphorous, Nitrogen, Antimony, GaAs, AlGaAs, InGaAs, AlAs, InGaAlAs, InGaP, InGaNP, AlGaSb, InSb, GaP, AlSb, GaSb, AlP, AlAs, and binary, ternary and quaternary combinations thereof, and wherein said substrate is chosen from one of Si, SiC, SiO2, sapphire, GaAs, and Ge.
10. The transistor of claim 1 wherein said semiconductor material is chosen from one of or a composite of Indium, Phosphorous, Aluminum, Antimony, InP, InAlP, InGaP, InGaAs, InAlAs, InSb, InAs, AlSb, GaSb, AlP, AlAs, and binary, ternary and quaternary combinations thereof, and wherein said substrate is chosen from one of GaAs, InP, Si, SiC, SiO2, and sapphire.
11. The transistor of claim 1 wherein said semiconductor material is chosen from one of or a composite of Silicon, Germanium, Carbon, Oxygen, SiGe, SiGeC, SiO2, SiC, sapphire, and binary, ternary and quaternary combinations thereof, and wherein said substrate is chosen from one of Si, SiC, sapphire, and SiO2.
12. The transistor of claim 1 wherein said semiconductor material is chosen from one of or a composite of Gallium, Nitrogen, Aluminum, Indium, Silicon, Carbon, Germanium, GaN, AlGaN, InGaN, InN, AlN, InAlGaN, SiC, SiGeC, Si, sapphire, and binary, ternary and quaternary combinations thereof, and wherein said substrate is chosen from one of Si, SiC, sapphire, and SiO2.
13. The transistor of claim 1 wherein said transistor is a depletion-mode (D-mode) FET.
14. The transistor of claim 1 wherein said transistor is an enhancement-mode (E-mode) FET.
15. The transistor of claim 1 wherein said transistor comprises three terminals, including a source, a drain, and a gate electrode.
16. The transistor of claim 1 wherein said transistor comprises four terminals, including a source, a drain, a gate, and a substrate contact electrode.
17. The transistor of claim 1 wherein said transistor comprises two terminals, including a source and a drain that share a common contact, and a separate gate electrode.
18. The transistor of claim 1 wherein said transistor includes at least one sidewall spacer to reduce a gate length.
19. The transistor of claim 1 wherein said transistor includes a plurality of gate electrodes chosen from one of a dependent electrode, an independent electrode, and a combination thereof.
20. The transistor of claim 1 wherein said material stack includes a buried channel and a first barrier layer positioned thereon, and wherein said fin comprises a second barrier layer positioned on said first barrier layer.
21. The transistor of claim 1 wherein said material stack includes a bulk channel and a first barrier layer positioned thereon, and wherein said fin comprises a second barrier layer positioned on said first barrier layer.
22. The transistor of claim 1 wherein said material stack includes a substrate, a buffer layer positioned on said substrate, a buried channel layer positioned on said buffer layer and at least one barrier layer positioned on said buried channel layer, and wherein said fin terminates within one of the at least one barrier layer, the buffer layer, and the substrate.
23. The transistor of claim 22 further comprising an optional ohmic contact layer positioned on top of said at least one barrier layer, said ohmic contact layer formed during one of, during a growth sequence of said at least one barrier layer, one buried channel layer and said at least one buffer layer, and after a growth sequence of said at least one barrier layer, one buried channel layer and said at least one buffer layer as an overgrown layer.
24. The transistor of claim 21 wherein said gate electrode is positioned directly on said second barrier layer.
25. The transistor of claim 21 further comprising an overgrown barrier layer positioned on said at least one barrier layer.
26. The transistor of claim 21 further comprising a gate dielectric layer positioned on said barrier layers, and wherein said gate electrode is positioned directly on said gate dielectric layer.
27. The transistor of claim 21 further comprising an overgrown barrier layer positioned on said at least one barrier layer and a gate dielectric layer positioned on said overgrown barrier layer, and wherein said gate electrode is positioned directly on said gate dielectric layer.
28. The transistor of claim 1 wherein said material stack includes a substrate, at least one buffer layer positioned on said substrate, and at least one bulk channel layer positioned on said at least one buffer layer, and wherein said fin terminates within one of said at least one bulk channel layer, said at least one buffer layer, and said substrate.
29. The transistor of claim 28 further comprising an optional ohmic contact layer positioned on top of said at least one bulk channel layer, said ohmic contact layer formed during one of during a growth sequence of said at least one bulk channel layer and said at least one buffer layer, and after a growth sequence of said at least one bulk channel layer and said at least one buffer layer as an overgrown layer.
30. The transistor of claim 28 wherein said gate electrode is positioned directly on said bulk channel.
31. The transistor of claim 30 wherein said gate electrode is formed with the use of a gate recess.
32. The transistor of claim 30 wherein said gate electrode is formed without the use of a gate recess.
33. The transistor of claim 28 further comprising an overgrown barrier layer positioned on said bulk channel layer.
34. The transistor of claim 28 further comprising a gate dielectric layer positioned on said bulk channel layer, and wherein said gate electrode is positioned directly on said gate dielectric layer.
35. The transistor of claim 28 further comprising an overgrown barrier layer positioned on said bulk channel layer and a gate dielectric layer positioned on said overgrown barrier layer, and wherein said gate electrode is positioned directly on said gate dielectric layer.
36. The transistor of claim 1 wherein said transistor is chosen from one of a MESFET, a MISFET, a MOSFET, a JFET, a planar-doped barrier field-effect transistor, a pHEMT, a HEMT, a MODFET, a mHEMT, a HIGFET, and a HFET.
37. The transistor of claim 36 wherein said transistor is chosen from one of a single-heterojunction transistor and a multi-heterojunction transistor.
38. The transistor of claim 1 wherein said gate dielectric material is chosen from one of an oxide of Silicon, a nitride of Silicon, an oxide of Tantalum (such as Ta2O5), an oxide of Titanium, an oxide of Hafnium, an oxide of Zirconium, an oxide of Aluminum, a perovskite, PZT, and BST.
39. A multi-gate fin-field effect transistor, comprising:
a substrate stack including a channel, wherein said channel is chosen from one of a buried channel and a bulk channel;
a fin of semiconductor material positioned on said substrate stack, said fin including first and second opposing side surfaces; and
a gate electrode positioned on said first and second opposing side surfaces of said fin.
40. A multi-gate fin-field effect transistor, comprising:
a substrate stack including a non-inverting channel layer;
a fin of semiconductor material positioned on said substrate stack, said fin including first and second opposing side surfaces; and
a gate electrode positioned on said first and second opposing side surfaces of said fin.
41. A multi-gate fin-field effect transistor, comprising:
a substrate stack including a channel layer that is depleted during operation;
a fin of semiconductor material positioned on said substrate stack, said fin including first and second opposing side surfaces; and
a gate electrode positioned on said first and second opposing side surfaces of said fin.
42. A multi-gate fin-field effect transistor, comprising:
a substrate stack including a channel layer that is depleted during operation;
a fin of semiconductor material positioned on said substrate stack, said fin including first and second opposing side surfaces; and
a gate electrode positioned on said first and second opposing side surfaces of said fin.
43. The transistor of claim 21 wherein said gate electrode is formed with the use of a gate recess.
44. The transistor of claim 21 wherein said gate electrode is formed without the use of a gate recess.