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1. US20030172233 - Plural station memory data sharing system

Office
United States of America
Application Number 10129173
Application Date 08.05.2003
Publication Number 20030172233
Publication Date 11.09.2003
Grant Number 7032080
Grant Date 18.04.2006
Publication Kind B2
IPC
G06F 12/00
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
G06F 15/16
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
G06F 15/17
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
163Interprocessor communication
17using an input/output type connection, e.g. channel, I/O port
G06F 1/14
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
04Generating or distributing clock signals or signals derived directly therefrom
14Time supervision arrangements, e.g. real time clock
G06F 13/00
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 15/167
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
163Interprocessor communication
167using a common memory, e.g. mailbox
CPC
H04L 12/417
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
28characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
40Bus networks
407with decentralised control
417with deterministic access, e.g. token passing
H04J 3/0652
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
JMULTIPLEX COMMUNICATION
3Time-division multiplex systems
02Details
06Synchronising arrangements
0635Clock or time synchronisation in a network
0638Clock or time synchronisation among nodes; Internode synchronisation
0652Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP]
H04L 69/28
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
69Application independent communication protocol aspects or techniques in packet data networks
28Timer mechanisms used in protocols
Applicants Step Technica Co., Ltd.
Koyo Electronics Industries Co. Ltd.
Inventors Mugitani Tomihiro
Natsui Toshiki
Agents Glenn Michael A.
Glenn Patent Group
Priority Data 2000265396 01.09.2000 JP
Title
(EN) Plural station memory data sharing system
Abstract
(EN)

A plural station memory data sharing system in which packets are sent/received between plural stations interconnected through communication lines. Each station has a unique station address value, and the time is made to correspond to each station address value. The internal clock (39) in each station indicates the same time and circulates from time T00 to an upper limit time TM. When the internal clock (39) indicates a time corresponding to the station address value of a station, data stored in a memory at the address position corresponding to the station address value is buried in a packet and the packet is sent through a communication line. An allowance time error sensing circuit (34) compares the calculated correct time of the internal clock of the station and the time indicated by the internal clock, If the error is out of an allowance range, the internal clock (39) is forcedly calibrated to the correct time.