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1. US6133961 - Architecture with centralized single memory for the transfer of video images

Office United States of America
Application Number 08776384
Application Date 21.04.1997
Publication Number 6133961
Publication Date 17.10.2000
Grant Number 6133961
Grant Date 17.10.2000
Publication Kind A
IPC
H04N 5/46
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
NPICTORIAL COMMUNICATION, e.g. TELEVISION
5Details of television systems
44Receiver circuitry
46for receiving on more than one standard at will
G06F 13/36
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
36for access to common bus or bus system
G06T 1/60
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
1General purpose image data processing
60Memory management
G09G 5/00
GPHYSICS
09EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
5Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
G09G 5/36
GPHYSICS
09EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
5Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
36characterised by the display of individual graphic patterns using a bit-mapped memory
G09G 5/39
GPHYSICS
09EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
5Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
36characterised by the display of individual graphic patterns using a bit-mapped memory
39Control of the bit-mapped memory
CPC
G09G 5/39
GPHYSICS
09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
5Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
36characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
39Control of the bit-mapped memory
G06T 1/60
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
1General purpose image data processing
60Memory management
G09G 5/36
GPHYSICS
09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
5Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
36characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
G09G 2340/10
GPHYSICS
09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
2340Aspects of display data processing
10Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
Applicants Thomson Broadcast Systems
Inventors Bourre Thierry
Labranche Patrick
Rebiai Mohamed
Bruhat Patrice
Agents Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Priority Data 95006752 08.06.1995 FR
Title
(EN) Architecture with centralized single memory for the transfer of video images
Abstract
(EN)

The invention relates to an architecture making it possible to store and transfer still or moving video images, the said architecture comprising at least one input circuit (E1, E2, . . . , En) allowing access for data intended to make up video images, a memory area (M) making it possible to store video images, at least one video image output circuit (S1, S2, . . . , Sj) and a video bus (B) intended to provide for the transfer of information between the memory area (M), the input circuit and the output circuit, characterized in that the memory area (M) is a general-purpose memory and in that the video bus (B) has a width L greater than or equal to the width of the memory area (M). PAL The general-purpose memory is operated in a centralized manner by a control circuit (CTRL). PAL The invention applies to computer platforms dedicated to the transfer of Broadcast quality images or alternatively to video devices for built-up image animation. The architecture according to the invention can also comprise video image processing circuits (T1, T2, . . . , Tn)