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1. US5696917 - Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory

Office United States of America
Application Number 08253499
Application Date 03.06.1994
Publication Number 5696917
Publication Date 09.12.1997
Grant Number 5696917
Grant Date 09.12.1997
Publication Kind A
IPC
G06F 12/00
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
G06F 12/06
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
06Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/08
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
G11C 7/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
CPC
G06F 12/08
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
G06F 12/0607
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
0607Interleaved addressing
G06F 2212/2022
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
20Employing a main memory using a specific memory technology
202Non-volatile memory
2022Flash memory
G11C 7/1045
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1015Read-write modes for single port memories, i.e. having either a random port or a serial port
1045Read-write mode select circuits
G11C 7/1072
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1072for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
Y02D 10/13
Applicants Intel Corporation
Inventors Mills Duane R.
Dipert Brian Lyn
Sambandan Sachidanandan
McCormick Bruce
Pashley Richard D.
Agents Blakely, Sokoloff, Taylor & Zafman
Title
(EN) Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
Abstract
(EN)

An asynchronous nonvolatile memory includes a plurality of individual memory components. A burst read operation references consecutive addresses beginning with a first address, wherein the consecutive addresses are not located in a same memory component. A method of performing a burst read operation in the asynchronous nonvolatile memory includes the step of providing the first address as a current address to the plurality of individual components. A current page identified by m higher order bits of the current address is selected. Each of the individual memory components senses a location identified by the m higher order bits. An output of a selected individual memory component is enabled in accordance with n lower bits of the current address. A consecutive subsequent address is provided, wherein the current address becomes a preceding address and the consecutive subsequent address becomes the current address. The output of another selected individual memory component identified by the n lower order bits of the current address is enabled without generating wait states, if the current and preceding addresses identify a same page. The process of providing consecutive subsequent addresses and enabling the output of a memory component identified by the n lower order bits is repeated as long as the current and preceding addresses identify the same page.