Processing

Please wait...

Settings

Settings

1. US5063579 - Scaler for synchronous digital clock

Office United States of America
Application Number 07524398
Application Date 11.05.1990
Publication Number 5063579
Publication Date 05.11.1991
Grant Number 5063579
Grant Date 05.11.1991
Publication Kind A
IPC
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
21
Details of pulse counters or frequency dividers
38
Starting, stopping, or resetting the counter
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
40
Gating or clocking signals applied to all stages, i.e. synchronous counters
48
with a base or radix other than a power of two
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
40
Gating or clocking signals applied to all stages, i.e. synchronous counters
50
using bi-stable regenerative trigger circuits
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
64
with a base or radix other than a power of two
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
64
with a base or radix other than a power of two
66
with a variable counting base, e.g. by presetting or by adding or suppressing pulses
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
64
with a base or radix other than a power of two
68
with a base which is a non-integer
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
16
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
16
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
18
using a frequency divider or counter in the loop
197
a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H03K 21/38
H03K 23/48
H03K 23/00
H03K 23/50
H03K 23/64
H03K 23/66
CPC
H03K 23/507
H03K 23/667
H03K 23/68
Applicants Northern Telecom Limited
Inventors Sasaki Lawrence H.
Chan Sun-Shiu D.
Agents Mowle John E.
Title
(EN) Scaler for synchronous digital clock
Abstract
(EN)

A scaler comprising a plurality of flip-flops, varies its frequency division to correct phase by 0.5 clock cycle. Each flip-flop is continuously and synchronously responsive to either a rising or a falling edge of the clock pulses. Normally, the scaler's state transits along one of two loops, which generate output pulses having identical repetition rates. When a control signal is applied, the scaler's state transits from one loop to the other, generating at least one output at an alternative repetition rate. The alternative repetition rate is either lower or higher than the identical repetition rate by an integral number of half cycles of the input clock pulses. Where there are two control signals, a lower or higher alternative repetition rate can be selected. Since the flip-flops are responsive to either edge of the clock pulses without clock gating interruptions, there is no jitter and the scaler's robustness is improved. Also the clock frequency can be effectively halved.