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1. US20220075624 - ALTERNATE PATH FOR BRANCH PREDICTION REDIRECT

Office
United States of America
Application Number 17012833
Application Date 04.09.2020
Publication Number 20220075624
Publication Date 10.03.2022
Publication Kind A1
IPC
G06F 9/38
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
G06F 9/30
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/48
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
48Program initiating; Program switching, e.g. by interrupt
G06F 12/1027
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
1027using associative or pseudo-associative address translation means, e.g. translation look-aside buffer
CPC
G06F 9/3861
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3861Recovery, e.g. branch miss-prediction, exception handling
G06F 9/3844
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
3842Speculative instruction execution
3844using dynamic prediction, e.g. branch history table
G06F 9/30079
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30076to perform miscellaneous control operations, e.g. NOP
30079Pipeline control instructions
G06F 12/1027
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
1027using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 9/3009
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30076to perform miscellaneous control operations, e.g. NOP
3009Thread control instructions
G06F 9/4843
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
48Program initiating; Program switching, e.g. by interrupt
4806Task transfer initiation or dispatching
4843by program, e.g. task dispatcher, supervisor, operating system
Applicants ADVANCED MICRO DEVICES, INC.
Inventors Ashok T. VENKATACHAR
Robert COHEN
Steven R. HAVLIR
Aparna Chandrashekhar MANDKE
Tzu-Wei LIN
Bhawna NAYAK
Title
(EN) ALTERNATE PATH FOR BRANCH PREDICTION REDIRECT
Abstract
(EN)

Branch prediction circuitry predicts an outcome of a branch instruction. A pipeline circuitry processes instructions along a first path from a predicted branch of the branch instruction. The instructions along the first path are processed concurrently with processing instructions along a second path from an unpredicted branch of the branch instruction. Information representing the state of the second portion while processing the second path is stored in one or more buffers. The instructions are processed along the second path using the information stored in the buffers in response to a misprediction of the outcome of the branch instruction. In some cases, the branch prediction circuitry determines a confidence level for the predicted outcome and the instructions along the second path from the unpredicted branch are processed in response to the confidence level being below a threshold confidence.


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