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1. US20220012397 - AUTOMATED ASSISTED CIRCUIT VALIDATION

Office
United States of America
Application Number 17370976
Application Date 08.07.2021
Publication Number 20220012397
Publication Date 13.01.2022
Publication Kind A1
IPC
G06F 30/367
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design
30Circuit design
36Circuit design at the analogue level
367Design verification, e.g. using simulation, simulation program with integrated circuit emphasis , direct methods or relaxation methods
G06F 30/398
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design
30Circuit design
39Circuit design at the physical level
398Design verification or optimisation, e.g. using design rule check , layout versus schematics or finite element methods
G06F 30/3953
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design
30Circuit design
39Circuit design at the physical level
394Routing
3953detailed
CPC
G06F 30/3953
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design [CAD]
30Circuit design
39Circuit design at the physical level
394Routing
3953detailed
G06F 30/367
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design [CAD]
30Circuit design
36Circuit design at the analogue level
367Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/398
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design [CAD]
30Circuit design
39Circuit design at the physical level
398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Applicants Tektronix, Inc.
Inventors David Everett Burgess
Title
(EN) AUTOMATED ASSISTED CIRCUIT VALIDATION
Abstract
(EN)

A method comprising categorizing nodes of a fabricated circuit as being priority nodes and nodes as being inferior nodes; evaluating a first priority node by automatically designating for verification the first priority node, and ascertaining whether a measured signal from the first priority node meets a pass-fail criterion for the first priority node; evaluating, when the measured signal from the first priority node meets the pass-fail criterion, a second priority node by automatically designating for verification the second priority node, and ascertaining whether a measured signal from the second priority node meets a pass-fail criterion for the second priority node; and evaluating, when the measured signal from the first priority node does not meet the pass-fail criterion, a first inferior node, by automatically designating for verification the first inferior node, and ascertaining whether a measured signal from the first inferior node meets a pass-fail criterion for the first inferior node.


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