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1. US11176295 - Matched net and device analysis based on parasitics

Office
United States of America
Application Number 16935296
Application Date 22.07.2020
Publication Number 11176295
Publication Date 16.11.2021
Grant Number 11176295
Grant Date 16.11.2021
Publication Kind B1
IPC
G06F 30/327
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design
30Circuit design
32Circuit design at the digital level
327Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
CPC
G06F 30/327
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design [CAD]
30Circuit design
32Circuit design at the digital level
327Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Applicants Diakopto, Inc.
Inventors Maxim Ershov
Agents Marc P. Schuyler
Title
(EN) Matched net and device analysis based on parasitics
Abstract
(EN)

A computer/software tool for electronic design automation (EDA) extracts parasitics from a post-layout netlist file for an integrated circuit (IC) design and uses these parasitics to model circuit behavior specifically to assess matching of reciprocal objects of a matched circuit. The computer/software tool generates a visual display based on the calculated design characteristics; for example, in one embodiment, asymmetry can be color-coded to permit a designer to visualize sources of matching problems base on mismatched parasitics. In other embodiments, the parasitics, structural elements and/or results can be filtered and/or processed, e.g., so as to provide EDA driven assistance to reduce excessive sensitivity to certain parasitics, and to minimize net and device systematic (layout-based) mismatch.