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1. US20210225416 - SYSTEM FOR IMPLEMENTING SHARED LOCK FREE MEMORY IMPLEMENTING COMPOSITE ASSIGNMENT

Office
United States of America
Application Number 17262365
Application Date 24.07.2019
Publication Number 20210225416
Publication Date 22.07.2021
Publication Kind A1
IPC
G11C 7/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
22Read-write timing or clocking circuits; Read-write control signal generators or management
H03K 19/20
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
20characterised by logic function, e.g. AND, OR, NOR, NOT circuits
CPC
G11C 7/22
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
G11C 7/1012
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
1012Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
H03K 19/20
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
20characterised by logic function, e.g. AND, OR, NOR, NOT circuits
G11C 7/1051
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
G11C 7/1078
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
Applicants JERUSALEM COLLEGE OF TECHNOLOGY
Inventors Shimon MIZRAHI
Raphael Berakhael YEHEZKAEL
Ruben ATTIA
Erez LAX
Devora BERLOWITZ
Moshe GOLDSTEIN
David DAYAN
Title
(EN) SYSTEM FOR IMPLEMENTING SHARED LOCK FREE MEMORY IMPLEMENTING COMPOSITE ASSIGNMENT
Abstract
(EN)

It is an object of the disclosed technique to provide a novel method and system for shared concurrent access to a memory cell. In accordance with the disclosed technique, there is thus provided a system for shared concurrent access to a memory cell, which includes at least one shared memory cell, an evaluator and a plurality of processing agents coupled to the input of the evaluator. The evaluator is further coupled with the at least one memory cell. The evaluator is configured to evaluate an expression for performing multiple concurrent composite assignments on the at least one shared memory cell. The evaluator further allows each of the plurality of processing agents to perform concurrent composite assignments on the at least one shared memory cell. The composite assignments do not include a read operation of the at least one shared memory cell by the plurality of processing agents.


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