Processing

Please wait...

Settings

Settings

Goto Application

1. US20210096862 - BIT WIDTH RECONFIGURATION USING A SHADOW-LATCH CONFIGURED REGISTER FILE

Office
United States of America
Application Number 16585817
Application Date 27.09.2019
Publication Number 20210096862
Publication Date 01.04.2021
Publication Kind A1
IPC
G06F 9/30
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
CPC
G06F 9/3013
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30098Register arrangements
3012Organisation of register space, e.g. banked or distributed register file
3013according to data content, e.g. floating-point registers, address registers
G06F 9/30101
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30098Register arrangements
30101Special purpose registers
Applicants ADVANCED MICRO DEVICES, INC.
Inventors Arun A. NAIR
Todd BAUMGARTNER
Michael ESTLICK
Erik SWANSON
Title
(EN) BIT WIDTH RECONFIGURATION USING A SHADOW-LATCH CONFIGURED REGISTER FILE
Abstract
(EN)

A processor includes a front-end with an instruction set that operates at a first bit width and a floating point unit coupled to receive the instruction set in the processor that operates at the first bit width. The floating point unit operates at a second bit width and, based upon a bit width assessment of the instruction set provided to the floating point unit, the floating point unit employs a shadow-latch configured floating point register file to perform bit width reconfiguration. The shadow-latch configured floating point register file includes a plurality of regular latches and a plurality of shadow latches for storing data that is to be either read from or written to the shadow latches. The bit width reconfiguration enables the floating point unit that operates at the second bit width to operate on the instruction set received at the first bit width.

Also published as