Processing

Please wait...

Settings

Settings

Goto Application

1. US20200177194 - Fractional frequency synthesis by sigma-delta modulating frequency of a reference clock

Office United States of America
Application Number 16205308
Application Date 30.11.2018
Publication Number 20200177194
Publication Date 04.06.2020
Publication Kind A1
IPC
H03L 7/197
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
18using a frequency divider or counter in the loop
197a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
CPC
H03L 7/1976
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
18using a frequency divider or counter in the loop
197a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
1974for fractional frequency division
1976using a phase accumulator for controlling the counter or frequency divider
Applicants Ciena Corporation
Inventors Sadok Aouini
Matthew Mikkelsen
Naim Ben-Hamida
Mahdi Parvizi
Tingjun Wen
Calvin Plett
Title
(EN) Fractional frequency synthesis by sigma-delta modulating frequency of a reference clock
Abstract
(EN)

A circuit includes a programmable frequency divider which receives a high-speed clock, fin, as an input and which provides a modulated reference clock as an output; a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock and to control an average frequency of the modulated reference clock; and an integer-N Phase Lock Loop (PLL) which receives the modulated reference clock and outputs a clock output.

Also published as