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1. US20190044764 - Multi-level signaling in memory with wide system interface

Office
United States of America
Application Number 15854600
Application Date 26.12.2017
Publication Number 20190044764
Publication Date 07.02.2019
Grant Number 10425260
Grant Date 24.09.2019
Publication Kind B2
IPC
H04L 25/49
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25Baseband systems
38Synchronous or start-stop systems, e.g. for Baudot code
40Transmitting circuits; Receiving circuits
49using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels
G11C 7/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
CPC
G11C 7/1048
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1048Data bus control circuits, e.g. precharging, presetting, equalising
H04L 25/4917
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25Baseband systems
38Synchronous or start-stop systems, e.g. for Baudot code
40Transmitting circuits; Receiving circuits
49using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; ; Baseband coding techniques specific to data transmission systems
4917using multilevel codes
G11C 7/1057
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
1057Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
G11C 7/1084
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
1084Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
G11C 7/1096
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
1096Write circuits, e.g. I/O line write drivers
H04L 25/4921
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25Baseband systems
38Synchronous or start-stop systems, e.g. for Baudot code
40Transmitting circuits; Receiving circuits
49using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; ; Baseband coding techniques specific to data transmission systems
4917using multilevel codes
4919using balanced multilevel codes
4921using quadrature encoding, e.g. carrierless amplitude-phase coding
Applicants Micron Technology, Inc.
Inventors Timothy M. Hollis
Markus Balb
Ralf Ebert
Agents Holland & Hart LLP
Title
(EN) Multi-level signaling in memory with wide system interface
Abstract
(EN)

Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.