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1. US20190026237 - COMPUTATIONAL ARRAY MICROPROCESSOR SYSTEM WITH VARIABLE LATENCY MEMORY ACCESS

Office United States of America
Application Number 15920150
Application Date 13.03.2018
Publication Number 20190026237
Publication Date 24.01.2019
Publication Kind A1
IPC
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
16
for access to memory bus
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
18
in which a programme is changed according to experience gained by the computer itself during a complete run; Learning machines
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
10
Complex mathematical operations
16
Matrix or vector computation
G06F 13/16
G06F 3/06
G06F 15/18
G06F 17/16
CPC
G06F 13/1642
G06F 13/1663
G06F 13/1689
G06F 15/18
G06F 17/16
G06F 3/0613
Applicants Tesla, Inc.
Inventors Emil Talpes
Peter Joseph Bannon
Kevin Altair Hurd
Title
(EN) COMPUTATIONAL ARRAY MICROPROCESSOR SYSTEM WITH VARIABLE LATENCY MEMORY ACCESS
Abstract
(EN)

A microprocessor system comprises a computational array and a hardware arbiter. The computational array includes a plurality of computation units. Each of the plurality of computation units operates on a corresponding value addressed from memory. The hardware arbiter is configured to control issuing of at least one memory request for one or more of the corresponding values addressed from the memory for the computation units. The hardware arbiter is also configured to schedule a control signal to be issued based on the issuing of the memory requests.