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1. US20190026078 - Accelerated mathematical engine

Office
United States of America
Application Number 15710433
Application Date 20.09.2017
Publication Number 20190026078
Publication Date 24.01.2019
Grant Number 10671349
Grant Date 02.06.2020
Publication Kind B2
IPC
G06K 9/00
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G06F 7/575
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06COMPUTING; CALCULATING OR COUNTING
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38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
57Arithmetic logic units , i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483-G06F7/556174
575Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
G06T 1/20
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TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
1General purpose image data processing
20Processor architectures; Processor configuration, e.g. pipelining
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G06F 7/52
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52Multiplying; Dividing
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48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
50Adding; Subtracting
CPC
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48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
50Adding; Subtracting
G06F 7/575
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7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
57Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 - G06F7/556 or for performing logical operations
575Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
G06F 7/52
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48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
52Multiplying; Dividing
G06F 7/5443
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
544for evaluating functions by calculation
5443Sum of products
G06F 15/80
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06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
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G06F 17/16
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
17Digital computing or data processing equipment or methods, specially adapted for specific functions
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16Matrix or vector computation ; , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
Applicants Tesla, Inc.
Inventors Peter Joseph Bannon
Kevin Altair Hurd
Emil Talpes
Agents Knobbe, Martens, Olson & Bear, LLP
Title
(EN) Accelerated mathematical engine
Abstract
(EN)

Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.