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1. (US20190026078) ACCELERATED MATHEMATICAL ENGINE

Office : United States of America
Application Number: 15710433 Application Date: 20.09.2017
Publication Number: 20190026078 Publication Date: 24.01.2019
Publication Kind : A1
IPC:
G06F 7/575
G06T 1/20
G06F 7/50
G06F 7/52
G06F 15/80
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
7
Methods or arrangements for processing data by operating upon the order or content of the data handled
38
Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48
using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
57
Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483-G06F7/556174
575
Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
T
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
1
General purpose image data processing
20
Processor architectures; Processor configuration, e.g. pipelining
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
7
Methods or arrangements for processing data by operating upon the order or content of the data handled
38
Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48
using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
50
Adding; Subtracting
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
7
Methods or arrangements for processing data by operating upon the order or content of the data handled
38
Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48
using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
52
Multiplying; Dividing
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
76
Architectures of general purpose stored programme computers
80
comprising an array of processing units with common control, e.g. single instruction multiple data processors
CPC:
G06F 15/80
G06F 7/50
G06F 7/52
G06F 7/575
G06T 1/20
Applicants: Tesla, Inc.
Inventors: Peter Joseph BANNON
Kevin Altair HURD
Emil TALPES
Priority Data:
Title: (EN) ACCELERATED MATHEMATICAL ENGINE
Abstract: front page image
(EN)

Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.