Processing

Please wait...

Settings

Settings

1. US20180315607 - Confined and scalable helmet

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

Claims

1. A system comprising:
a first gate and a first contact both on a first fin;
a second gate and a second contact both on a second fin; and
an interlayer dielectric (ILD) portion between the first and second contacts;
wherein (a) the first and second gates are intersected by a first axis that is substantially orthogonal to long axes of the first and second fins, (b) the first and second contacts and the ILD portion are intersected by a second axis that is substantially parallel to the first axis; and (c) the ILD portion includes a recess that comprises a cap layer including at least one of an oxide, a nitride, or a combination thereof;
wherein the cap layer is not monolithic with the ILD portion;
wherein the long axis of the first fin defines a length of the first fin, a short axis of the first fin defines a width of the first fin, the short axis is shorter than the long axis, and a height of the first fin is orthogonal to the long and short axes of the first fin.
2. The system of claim 1, wherein the recess includes an additional cap layer directly contacting the cap layer.
3. The system of claim 1, wherein the cap layer includes a parabolic bottom surface.
4. The system of claim 1, wherein:
the first and second fins are on a substrate;
a plane, which is parallel to a surface of the substrate, intersects the cap layer and the first gate;
the surface of the substrate is between the substrate and the first gate.
5. A method comprising:
forming first, second, and third replacement gate columns over a semiconductor fin;
forming a first interlayer dielectric (ILD) between the first and second columns and a second ILD between the second and third columns;
recessing a first portion of the first ILD to form a first recess between the first and second columns and recessing a second portion of the second ILD to form a second recess between the second and third columns;
forming a first oxide within the first recess and a second oxide within the second recess, the first and second oxides directly contacting each other;
planarizing the first and second oxides while the first and second oxides are within the first and second recesses, the planarized first and second oxides not directly contacting each other;
removing a portion of at least one of the first, second, or third replacement gate columns or combinations thereof, while the planarized first and second oxides are within the first and second recesses, to form a void; and
forming a gate within the void.
6. The method of claim 5 comprising:
removing at least a portion of the planarized first oxide and at least a portion of the first ILD to form an additional void; and
forming a contact for a transistor node within the additional void;
wherein the transistor node includes one of a source or a drain.
7. The method of claim 5 comprising;
forming a capping layer within the first and second recesses; and
planarizing the capping layer and forming planarized first and second portions of the capping layer within the first and second recesses, the planarized first and second portions of the capping layer not directly contacting each other.
8. The method of claim 7, comprising removing at least a portion of the planarized first portion of the capping layer to form the additional void.
9. The method of claim 7, wherein the capping layer includes at least one of an oxide, a nitride, or combination thereof.
10. A system comprising:
a first gate column, a first source contact column, and a first drain contact column all on a first semiconductor fin;
a second gate column, a second source contact column, and a second drain contact column all on a second semiconductor fin; and
a first interlayer dielectric (ILD) portion collinear with and between the first and second source contact columns and a second ILD portion collinear with and between the first and second drain contact columns;
wherein (a) the first gate column is collinear with the second gate column, the first source contact column is collinear with the second source contact column, and the first drain contact column is collinear with the second drain contact column; (b) the first ILD portion includes a first recess and the second ILD portion includes a second recess; and (c) the first recess includes a first oxide cap layer and the second recess includes a second oxide cap layer.
11. The system of claim 10, wherein the first oxide cap layer does not directly contact the second oxide cap layer.
12. The system of claim 11, wherein the first recess includes a first additional cap layer directly contacting the first oxide cap layer and the second recess includes a second additional cap layer directly contacting the second oxide cap layer.
13. The system of claim 12, wherein:
the first additional cap layer includes a substantially planar first top surface and the second additional cap layer includes a substantially planar second top surface; and
the substantially planar first top surface is coplanar with the substantially planar second top surface.
14. The system of claim 13, wherein the first additional cap layer includes at least one of an oxide, a nitride, or a combination thereof and the second additional cap layer includes at least one of an oxide, a nitride, or a combination thereof.
15. The system of claim 14, wherein the first oxide cap layer includes a bottom surface that is parabolic in shape.
16. The system of claim 15, wherein the bottom surface includes lateral portions that are above a middle portion of the bottom surface.
17. The system of claim 11 comprising a third ILD portion between the first source contact column and the first drain contact column; wherein the third ILD portion includes a third recess and the third recess includes a third oxide cap layer.
18. The system of claim 17, wherein a vertical axis intersects the third recess and the first semiconductor fin.
19. The system of claim 18, wherein the third recess includes a third additional cap layer that includes at least one of an oxide, a nitride, or a combination thereof.
20. The system of claim 19, wherein a horizontal plane intersects the first and third oxide cap layers.
21. The system of claim 19, wherein a horizontal plane intersects the first, second, and third oxide cap layers.
22. The system of claim 11, wherein a horizontal plane intersects the first and second oxide cap layers and the first gate column.
23. The system of claim 11, wherein the first and second ILD portions each include ILD 0.