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1. US20180150431 - Fast matrix multiplication and linear algebra by alternative basis

Office United States of America
Application Number 15823776
Application Date 28.11.2017
Publication Number 20180150431
Publication Date 31.05.2018
Grant Number 10387534
Grant Date 20.08.2019
Publication Kind B2
IPC
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
10
Complex mathematical operations
16
Matrix or vector computation
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
13
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
10
Complex mathematical operations
11
for solving equations
12
Simultaneous equations
G06F 17/16
H03M 13/00
G06F 9/30
G06F 17/12
CPC
G06F 9/30036
G06F 17/16
G06F 17/12
H03M 13/616
Applicants YISSUM RESEARCH DEVELOPMENT COMPANY OF THE HEBREW UNIVERSITY OF JERUSALEM LTD.
Inventors Oded Schwartz
Elaye Karstadt
Agents The Roy Gross Law Firm, LLC
Roy Gross
Title
(EN) Fast matrix multiplication and linear algebra by alternative basis
Abstract
(EN)

A computerized method comprising operating one or more hardware processor for receiving a first matrix and a second matrix. The hardware processor(s) are operated for determining a basis transformation, wherein the basis transformation is invertible to an inverted basis transformation. The hardware processor(s) are operated for computing an alternative basis first matrix by multiplying the first matrix by the basis transformation. The hardware processor(s) are operated for computing an alternative basis second matrix by multiplying the second matrix by the basis transformation. The hardware processor(s) are operated for performing a matrix multiplication of the alternative basis first matrix and the alternative basis second matrix, thereby producing an alternative basis multiplied matrix. The hardware processor(s) are operated for computing a multiplied matrix by multiplying the alternative basis multiplied matrix by the inverted basis transformation.