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1. US20160381809 - FACE-UP SUBSTRATE INTEGRATION WITH SOLDER BALL CONNECTION IN SEMICONDUCTOR PACKAGE

Office
United States of America
Application Number 15260249
Application Date 08.09.2016
Publication Number 20160381809
Publication Date 29.12.2016
Publication Kind A1
IPC
H05K 3/30
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
30Assembling printed circuits with electric components, e.g. with resistor
H05K 1/03
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
03Use of materials for the substrate
H01L 23/64
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for
64Impedance arrangements
H05K 3/40
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
40Forming printed elements for providing electric connections to or between printed circuits
CPC
H05K 3/303
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
30Assembling printed circuits with electric components, e.g. with resistor
303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
H05K 3/4007
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
40Forming printed elements for providing electric connections to or between printed circuits
4007Surface contacts, e.g. bumps
H05K 1/0306
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
03Use of materials for the substrate
0306Inorganic insulating substrates, e.g. ceramic, glass
H01L 23/645
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for ; , e.g. in combination with batteries
64Impedance arrangements
645Inductive arrangements
H05K 220/1003
Applicants QUALCOMM Incorporated
Inventors Daeik Daniel KIM
Jonghae KIM
Chengjie ZUO
Changhan Hobie YUN
Mario Francisco VELEZ
Robert Paul MIKULKA
Title
(EN) FACE-UP SUBSTRATE INTEGRATION WITH SOLDER BALL CONNECTION IN SEMICONDUCTOR PACKAGE
Abstract
(EN)

Systems and methods relate to a semiconductor package comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component and a first set of one or more package pads formed on a face of a glass substrate. The semiconductor package also includes a second or laminate substrate with a second set of one or more package pads formed on a face of the second or laminate substrate. Solder balls are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) can be coupled to a bottom side of the second or laminate substrate.


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BR112016021591This application is not viewable in PATENTSCOPE because the national phase entry has not been published yet or the national entry is issued from a country that does not share data with WIPO or there is a formatting issue or an unavailability of the application.