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1. (US20160006478) Apparatus and method to perform a double correlation
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Claims

1. An apparatus for performing a double correlation function on a received signal and a plurality of predetermined chip codes from a communication standard, the apparatus comprising:
a first plurality of logic gates configured as a multiplier unit operable to receive a signal sampled at a predetermined sampling frequency, and to perform predetermined multiplication operations on the input signal in accordance with the correlation function;
a first memory unit operable to receive and store multiplication values from the first plurality of logic gates;
a second memory unit having stored therein values from predetermined multiplication operations performed on the plurality of chip codes in accordance with the correlation function; and
a second plurality of logic gates configured as an adder unit to receive multiplication values outputted from the first memory unit and the second memory unit and to sum the multiplication values from the first memory unit taking into account the multiplication values from the second memory unit; and
a sign selection unit configured to assign a positive or negative sign to each value from the first plurality of logic gates dependent on the sign of an associated value stored in the second memory unit.
2. The apparatus according to claim 1, comprising a third plurality of logic gates configured as a result-adder unit operable to receive and sum values received from the second plurality of logic gates.
3. The apparatus according to claim 2, comprising a sequencer operable to select multiplication values associated with one of the chip codes stored in the second memory unit to be outputted to the second plurality of logic gates, whereby the second plurality of logic gates is operable to sum the multiplication values from the first memory unit taking into account the multiplication values for the selected chip code.
4. The apparatus according to claim 3, comprising a correlation value memory unit operable to receive and store the sum of the values from the third plurality of logic gates for the selected chip code, wherein the correlation value memory unit is configured to receive a selection signal from the sequencer to select a position in the correlation value memory unit to store the sum of the values from the third plurality of logic gates.
5. The apparatus according to claim 1, comprising an input sample memory configured to store therein the received sampled signal and to output sampled signal values to the first plurality of logic gates.
6. The apparatus according to claim 5, wherein the first plurality of logic gates is configured to perform a predetermined number of product calculations in parallel based on the number of chips in the chip code and wherein the input sample memory is configured to output a predetermined number of samples to the first plurality of logic gates based on the correlation function and the number of chips in the chip code.
7. The apparatus according to claim 5, wherein the first plurality of logic gates is configured to perform a predetermined product calculation and output the result to the first memory unit, wherein the input sample memory is configured to output samples to the first plurality of logic gates based on the correlation function.
8. The apparatus according to claim 7, wherein the first memory unit comprises a plurality of cells arranged in series, wherein each cell comprises an output for outputting a multiplication value, whereby the multiplication values from the plurality of cells are stored in series from the first plurality of logic gates and output in parallel.
9. The apparatus according to claim 8, wherein the number of cells and cell outputs is based on the number of chips in the chip code.
10. The apparatus according to claim 8, wherein each of the cells comprises a plurality of shift registers arranged in series.
11. The apparatus according to claim 8, comprising a third plurality of logic gates configured as a result-adder unit operable to receive and sum values received from the second plurality of logic gates wherein one of the cells is arranged to hold a value for a predetermined period of time dependent on a hold signal received from the sequencer while values are fed through the one cell.
12. The apparatus according to claim 8, wherein the second plurality of logic gates is operable to sum the multiplication values from the first memory unit when a predetermined number of multiplication values based on the number of chip codes are stored therein.
13. A receiver comprising:
an analog signal input for receiving an analog signal;
an analog-to-digital converter arranged to convert the received analog signal into a digital signal; and
a demodulator connected to the output of the an analog-to-digital converter; the demodulator comprising a sampler operable to sample the digital signal at a predetermined sampling frequency; and an apparatus according to any one of claims 1- 4, or 5- 12 arranged to receive the sampled signal.
14. A method for performing a double correlation function on a received signal and a plurality of predetermined chip codes from a communication standard, the method comprising the steps of:
receiving a signal sampled at a predetermined sampling frequency;
performing predetermined multiplication operations on the input signal in accordance with the correlation function;
storing multiplication values from the predetermined multiplication operations performed on the input signal in a first memory unit;
configuring a second memory unit having stored therein values from predetermined multiplication operations performed on the plurality of chip codes in accordance with the correlation function; and
summing the multiplication values from the first memory unit taking into account the multiplication values stored in the second memory unit; and
assigning a positive or negative sign to each value from the first plurality of logic gates dependent on the sign of an associated value stored in the second memory unit.