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1. US20160006478 - Apparatus and method to perform a double correlation

Office United States of America
Application Number 14769857
Application Date 21.02.2014
Publication Number 20160006478
Publication Date 07.01.2016
Grant Number 09660692
Grant Date 23.05.2017
Publication Kind B2
IPC
H04B 1/709
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
BTRANSMISSION
1Details of transmission systems, not covered by a single one of groups H04B3/-H04B13/123; Details of transmission systems not characterised by the medium used for transmission
69Spread spectrum techniques
707using direct sequence modulation
709Correlator structure
H04J 3/06
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
JMULTIPLEX COMMUNICATION
3Time-division multiplex systems
02Details
06Synchronising arrangements
CPC
H04B 1/709
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
BTRANSMISSION
1Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
69Spread spectrum techniques
707using direct sequence modulation
709Correlator structure
H04J 3/0611
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
JMULTIPLEX COMMUNICATION
3Time-division multiplex systems
02Details
06Synchronising arrangements
0602Systems characterised by the synchronising information used
0605Special codes used as synchronising signal
0611PN codes
Applicants Cascoda Limited
Inventors Wolfgang Bruchner
Agents Renner, Otto, Boisselle & Sklar, LLP
Priority Data 201303154 22.02.2013 GB
Title
(EN) Apparatus and method to perform a double correlation
Abstract
(EN)

An apparatus is described for performing a correlation function on a received signal and a plurality of predetermined chip codes from a communication standard. The apparatus comprising: a first plurality of logic gates configured as a multiplier unit operable to receive a signal sampled at a predetermined sampling frequency, and to perform predetermined multiplication operations on the input signal in accordance with the correlation function; a first memory unit operable to receive and store multiplication values from the first plurality of logic gates; a second memory unit having stored therein values from predetermined multiplication operations performed on the plurality of chip codes in accordance with the correlation function; and a second plurality of logic gates configured as an adder unit to receive multiplication values outputted from the first memory unit and the second memory unit and to sum the multiplication values from the first memory unit taking into account the multiplication values in the from the second memory unit.