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1. (US20140195829) Dynamically computing an electrical design point (EDP) for a multicore processor

Office : United States of America
Application Number: 13997757 Application Date: 13.03.2012
Publication Number: 20140195829 Publication Date: 10.07.2014
Grant Number: 09436245 Grant Date: 06.09.2016
Publication Kind : B2
Prior PCT appl.: Application Number:PCTUS2012028876 ; Publication Number: Click to see the data
IPC:
G06F 1/26
G06F 1/32
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
26
Power supply means, e.g. regulation thereof
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
26
Power supply means, e.g. regulation thereof
32
Means for saving power
Applicants: Malini K. Bhandaru
Intel Corporation
Eric J. Dehaemer
Jeremy J. Shrall
Inventors: Malini K. Bhandaru
Eric J. Dehaemer
Jeremy J. Shrall
Agents: Trop, Pruner & Hu, P.C.
Priority Data:
Title: (EN) Dynamically computing an electrical design point (EDP) for a multicore processor
Abstract: front page image
(EN)

In one embodiment, a multicore processor includes a controller to dynamically limit a maximum permitted turbo mode frequency of its cores based on a core activity pattern of the cores and power consumption information of a unit power table. In one embodiment, the core activity pattern can indicate, for each core, an activity level and a logic unit state of the corresponding core. Further, the unit power table can be dynamically computed based on a temperature of the processor. Other embodiments are described and claimed.


Also published as:
WO/2013/137860