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1. MYPI 20014342 - SYSTEM AND METHOD FOR SINGLE PIN RESET A MIXED SIGNAL INTEGRATED CIRCUIT.

Office
Malaysia
Application Number PI 20014342
Application Date 17.09.2001
Publication Number PI 20014342
Publication Date 19.03.2002
Publication Kind A
IPC
H03K 3/02
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02Generators characterised by the type of circuit or by the means used for producing pulses
Applicants Interdigital Madison Patent Holdings
Inventors DAVID LAWRENCE ALBEAN
Agents PATRICK MIRANDAH
Priority Data 09666021 19.09.2000 US
Title
(EN) SYSTEM AND METHOD FOR SINGLE PIN RESET A MIXED SIGNAL INTEGRATED CIRCUIT.
Abstract
(EN)
A SYSTEM (10) AND METHOD IS DESCRIBED FOR PROVIDING A SINGLE PIN RESET FOR A MIXED SIGNAL INTEGRATED CIRCUIT. THE SYSTEM (10) AND METHOD PROVIDES FOR A SINGLE RESET SIGNAL/PIN OF THE INTEGRATED CIRCUIT TO BE UTILIZED TO GENERATE ALL INTERNAL RESETS FOR THE ANALOG AND DIGITAL CIRCUITRY/SECTIONS OF THE MIXED SIGNAL INTEGRATED CIRCUIT. IN ONE FORM, A STATE MACHINE GENERATES A RESET SIGNAL (88) FOR A PHASE LOCKED LOOP SYNTHESIZER THAT IS UTILIZED TO GENERATE INTERNAL SYSTEM CLOCKS FOR THE ANALOG AND DIGITAL CIRCUITRY, AS WELL AS A DIGITAL RESET SIGNAL (88) THAT PROVIDES RESET SIGNALS TO THE VARIOUS DIGITAL SECTIONS CIRCUITRY OF THE INTEGRATED CIRCUIT. PREFERABLY, THE CHIP RESET SIGNAL (88) IS PROVIDED FOR A LONGER PERIOD OF TIME THAN THE PLL RESET SIGNAL (84) IN ORDER TO ASSURE THAT THE PLL IS RUNNING AND GENERATING CLOCKING SIGNALS BEFORE THE DIGITAL LOGIC IS CLOCKED.(FIG 4)