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1. (KR1020120023297) THREE-DIMENSIONAL SEMICONDUCTOR APPARATUS WHICH INCLUDES THREE-DIMENSIONALLY ARRANGED MEMORY CELLS AND A MANUFACTURING METHOD THEREOF

Office : Republic of Korea
Application Number: 1020100085647 Application Date: 01.09.2010
Publication Number: 1020120023297 Publication Date: 13.03.2012
Grant Number: Grant Date: 14.02.2017
Publication Kind : B1
IPC:
H01L 27/115
H01L 21/8247
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
112
Read-only memory structures
115
Electrically programmable read-only memories
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8246
Read-only memory structures (ROM)
8247
electrically-programmable (EPROM)
CPC:
H01L 21/28282
H01L 27/11551
H01L 27/11556
H01L 27/11578
H01L 27/11582
H01L 27/0688
Applicants: SAMSUNG ELECTRONICS CO., LTD.
삼성전자주식회사
삼성전자주식회사
Inventors: CHANG, SUNG IL
장성일
PARK, YOUNG WOO
박영우
LEE, JAE GOO
이재구
장성일
박영우
이재구
Agents: 권혁수
특허법인 고려
송윤호
오세준
Priority Data:
Title: (EN) THREE-DIMENSIONAL SEMICONDUCTOR APPARATUS WHICH INCLUDES THREE-DIMENSIONALLY ARRANGED MEMORY CELLS AND A MANUFACTURING METHOD THEREOF
(KO) 3차원 반도체 장치 및 그 제조 방법
Abstract: front page image
(EN) PURPOSE: A three-dimensional semiconductor apparatus and a manufacturing method thereof are provided to localize a region for charge storage, thereby solving a technical problem due to a charge spreading phenomenon. CONSTITUTION: A charge storage layer(CL) covers an opening part and an undercut region(107). The charge storage layer comprises vertical parts(VTP), horizontal parts(HRP), and connection parts(CNP). The space between the horizontal parts is filled with a tunnel insulating layer(TIL). The tunnel insulating layer includes extension parts arranges between the horizontal parts of the charge storage layer. A gap is formed between the horizontal parts. COPYRIGHT KIPO 2012
(KO) 3차원 반도체 장치 및 그 제조 방법이 제공된다. 이 장치는 차례로 적층된 전극들을 포함하면서 기판 상에 배치되는 전극 구조체, 전극 구조체를 관통하는 반도체 패턴들, 반도체 패턴들과 전극 구조체 사이에 개재되는 전하저장 패턴들, 그리고 전하저장 패턴들과 전극 구조체 사이에 개재되는 블록킹절연 패턴들을 포함한다. 블록킹 절연 패턴들 각각은 수평적으로 연장되어 반도체 패턴들 중의 복수의 것들의 주변에 배치되고, 전하저장 패턴들 각각은 수평적으로 분리되어 반도체 패턴들 중의 서로 다른 것들의 주변에 배치될 수 있다. 전하저장 패턴들 각각은 전극들과 반도체 패턴의 측벽들 사이로부터 수평적으로 연장되어 전극들의 수평면들 사이에 개재되는 수평부들을 구비할 수 있다.