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1. KR101036441* - SEMICONDUCTOR CHIP LAMINATE PACKAGE AND MANUFACTURING METHOD THEREOF CAPABLE OF IMPROVING THE ACCURACY OF A CHIP ALIGNMENT

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Office Republic of Korea
Application Number 1020100131939
Application Date 21.12.2010
Publication Number 101036441*
Publication Date 17.05.2011
Grant Number 1010364410000
Grant Date 17.05.2011
Publication Kind B1
IPC
H01L 23/10
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
02Containers; Seals
10characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H01L 23/12
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
CPC
H01L 23/488
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
488consisting of soldered ; or bonded; constructions
H01L 21/50
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
H01L 24/26
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
H01L 24/29
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
H01L 24/32
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
H01L 24/48
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
Inventors LEE, JAE HAK
이재학
SONG, JUN YEOB
송준엽
HA, TAE HO
하태호
LEE, CHANG WOO
이창우
Agents KOREA INSTITUTE OF MACHINERY & MATERIALS
김종관
권오식
박창희
Title
(EN) SEMICONDUCTOR CHIP LAMINATE PACKAGE AND MANUFACTURING METHOD THEREOF CAPABLE OF IMPROVING THE ACCURACY OF A CHIP ALIGNMENT
(KO) 반도체 칩 적층 패키지 및 그 제조 방법
front page image
Abstract
(EN)
PURPOSE: A semiconductor chip laminate package and a manufacturing method thereof are provided to simplify a process by self-alignment. CONSTITUTION: A planar chip is prepared(S10). The attachment surface of the chip is processed with a hydrophilic surface(S20). The other surface of the chip is processed with a hydrophobic surface(S30). The hydrophilic surface processed part is contacted with the exposed part of the chip and is aligned(S40). The chip is fixed by applying heat or pressure(S50). A wire is attached to the connection unit of the aligned chip(S60). COPYRIGHT KIPO 2011

(KO)
본 발명은 반도체 칩 적층 패키지 및 그 제조 방법에 관한 것으로서, 더욱 상세하게, 복수개의 칩을 정밀한 장치 또는 작업 없이 빠르게 정렬 및 본딩 가능하여 생산성을 향상할 수 있는 반도체 칩 적층 패키지 및 그 제조 방법에 관한 것이다.

Also published as
SG181416
US20130256911
WO/2012/086871
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